155 research outputs found

    Executable Specs: What Makes One, and How are They Used?

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    Model-based systems development relies upon the concept of an executable specification. A survey of published literature shows a wide range of definitions for executable specifications [1-10]. In this paper, we attempt to codify the essential starting elements for a complete executable specification-based design flow. A complete executable specification that includes a functional model as well as test cases, in addition to a traditional prose document, is needed to transfer requirements from a customer to a supplier, or from a systems engineer to electrical hardware and software engineers. In the complete form demonstrated here, sub-components of a functionally-decomposed system manifest as modular reuse blocks suitable for publication in functional libraries. The overarching definition provided by product architecture and by software architecture must also be harmoniously integrated with design and implementation. Using seven specific automotive examples, we illustrate effective ways in which executable specifications have been used in production-ready applications. Benefits of model-based development are captured, including earlier and more thorough testing, automatic document generation, and autocode generation

    State-of-art on permanent magnet brushless DC motor drives

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    Permanent magnet brushless DC (PMBLDC) motors are the latest choice of researchers due to their high efficiency, silent operation, compact size, high reliability and low maintenance requirements. These motors are preferred for numerous applications; however, most of them require sensorless control of these motors. The operation of PMBLDC motors requires rotor-position sensing for controlling the winding currents. The sensorless control would need estimation of rotor position from the voltage and current signals, which are easy to be sensed. This paper presents a state of art on PMBLDC motor drives with emphasis on sensorless control of these motors

    Variable Pathlength Cavity Spectroscopy Development of an Automated Prototype

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    ABSTRACT VARIABLE PATHLENGTH CAVITY SPECTROSCOPY DEVELOPMENT OF AN AUTOMATED PROTOTYPE by Ryan Andrew Schmeling The University of Wisconsin-Milwaukee, 2016 Under the Supervision of Professor Joseph H. Aldstadt III Spectroscopy is the study of the interaction of electromagnetic radiation (EMR) with matter to probe the chemical and physical properties of atoms and molecules. The primary types of analytical spectroscopy are absorption, emission, and scattering methods. Absorption spectroscopy can quantitatively determine the chemical concentration of a given species in a sample by the relationship described by Beer’s Law. Upon inspection of Beer’s Law, it becomes apparent that for a given analyte concentration, the only experimental variable is the pathlength. Over the past ~75 years, several approaches to physically increasing the pathlength have been reported in the literature. These have included not only larger cuvettes and novel techniques such as Differential Optical Absorption Spectroscopy, but also numerous designs that are based upon the creation of an optical cavity in which multiple reflections through the sample are made possible. The cavity-based designs range from the White Cell (1942) to Cavity Ring-Down Spectroscopy (O\u27Keefe and Deacon, 1998). In the White Cell approach, the incident beam is directed off-axis to repeatedly reflect concave mirror surfaces. Numerous variations of the White Cell design have been reported, and it has found wide application in infrared absorption spectroscopy in what have become to be known as “light pipes”. In the CRDS design, on the other hand, highly reflective dielectric mirrors situated for on-axis reflections result in the measurement of the exponential decay of trapped light that passes through the exit mirror. CRDS has proven over the past two decades to be a powerful technique for ultra-trace analysis (\u3c 10-15 g), with practical applications ranging from atmospheric monitoring of greenhouse gases to biomedical “breath screening” as a means to identify disease states. In this thesis, a novel approach to ultra-trace analysis by absorption spectroscopy is described. In this approach known as Variable Pathlength Cavity Spectroscopy (VPCS), a high finesse optical cavity is created by two flat, parallel, dielectric mirrors — one of which is rotating. Source light from a pulsed dye laser (488 nm) enters the optical cavity in the same manner as in Cavity Ring-Down Spectroscopy (CRDS), i.e., by passing through the cavity entrance mirror. However, unlike CRDS in which the mirrors are fixed, concave, and mechanically unaltered, the cavity exit mirror contains a slit (1.0 mm diameter) that is rotated at high speed on an axle, thereby transmitting a small fraction of the trapped light to a photomultiplier tube detector. In this approach, unlike CRDS, absorbance is measured directly. In previous prototype designs of the VPCS instrument, instrument control (alignment) and data acquisition and reduction were performed manually; these functions were both inefficient and tedious. Despite this, the VPCS was validated in proof of concept testing, as described with a previous prototype (Frost, 2011). Frost demonstrated that the pathlength enhancement increased 53-fold compared to single-pass absorption measurements in monitoring NO2 (g) at part-per-billion levels. The goal of the present work is to improve upon the previous prototype (“P4”) that required manual alignment, data collection, and data reduction by creating a completely automated version of VPCS — i.e., the “P5” prototype. By developing source code in LabVIEW™, demonstration that the VPCS can be completely controlled in an automated fashion is described. Computationally, a Field-Programmable Gate Array is used to automate the process of data collection and reduction in real-time. It is shown that the inputs and outputs of the P5 instrument can be continuously monitored, allowing for real-time triggering of the source laser, collection of all data, and reduction of the data to report absorbance. Furthermore, it is shown that the VPCS can be automatically aligned — also in real-time on the order of microseconds — to a high degree of precision by using servo-actuators that adjust the beam position based upon the input from a sensitive CCD camera. With the implementation of this hardware and LabVIEW code, more precise data collection and reduction is done. With this new fully automated design, the instrument characteristics (e.g., to include factors such as rotation speed, off-set angle, and pathlength variation) can improve the enhancement by ~130-fold vs. single-pass absorption measurements

    Energy-efficient embedded machine learning algorithms for smart sensing systems

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    Embedded autonomous electronic systems are required in numerous application domains such as Internet of Things (IoT), wearable devices, and biomedical systems. Embedded electronic systems usually host sensors, and each sensor hosts multiple input channels (e.g., tactile, vision), tightly coupled to the electronic computing unit (ECU). The ECU extracts information by often employing sophisticated methods, e.g., Machine Learning. However, embedding Machine Learning algorithms poses essential challenges in terms of hardware resources and energy consumption because of: 1) the high amount of data to be processed; 2) computationally demanding methods. Leveraging on the trade-off between quality requirements versus computational complexity and time latency could reduce the system complexity without affecting the performance. The objectives of the thesis are to develop: 1) energy-efficient arithmetic circuits outperforming state of the art solutions for embedded machine learning algorithms, 2) an energy-efficient embedded electronic system for the \u201celectronic-skin\u201d (e-skin) application. As such, this thesis exploits two main approaches: Approximate Computing: In recent years, the approximate computing paradigm became a significant major field of research since it is able to enhance the energy efficiency and performance of digital systems. \u201cApproximate Computing\u201d(AC) turned out to be a practical approach to trade accuracy for better power, latency, and size . AC targets error-resilient applications and offers promising benefits by conserving some resources. Usually, approximate results are acceptable for many applications, e.g., tactile data processing,image processing , and data mining ; thus, it is highly recommended to take advantage of energy reduction with minimal variation in performance . In our work, we developed two approximate multipliers: 1) the first one is called \u201cMETA\u201d multiplier and is based on the Error Tolerant Adder (ETA), 2) the second one is called \u201cApproximate Baugh-Wooley(BW)\u201d multiplier where the approximations are implemented in the generation of the partial products. We showed that the proposed approximate arithmetic circuits could achieve a relevant reduction in power consumption and time delay around 80.4% and 24%, respectively, with respect to the exact BW multiplier. Next, to prove the feasibility of AC in real world applications, we explored the approximate multipliers on a case study as the e-skin application. The e-skin application is defined as multiple sensing components, including 1) structural materials, 2) signal processing, 3) data acquisition, and 4) data processing. Particularly, processing the originated data from the e-skin into low or high-level information is the main problem to be addressed by the embedded electronic system. Many studies have shown that Machine Learning is a promising approach in processing tactile data when classifying input touch modalities. In our work, we proposed a methodology for evaluating the behavior of the system when introducing approximate arithmetic circuits in the main stages (i.e., signal and data processing stages) of the system. Based on the proposed methodology, we first implemented the approximate multipliers on the low-pass Finite Impulse Response (FIR) filter in the signal processing stage of the application. We noticed that the FIR filter based on (Approx-BW) outperforms state of the art solutions, while respecting the tradeoff between accuracy and power consumption, with an SNR degradation of 1.39dB. Second, we implemented approximate adders and multipliers respectively into the Coordinate Rotational Digital Computer (CORDIC) and the Singular Value Decomposition (SVD) circuits; since CORDIC and SVD take a significant part of the computationally expensive Machine Learning algorithms employed in tactile data processing. We showed benefits of up to 21% and 19% in power reduction at the cost of less than 5% accuracy loss for CORDIC and SVD circuits when scaling the number of approximated bits. 2) Parallel Computing Platforms (PCP): Exploiting parallel architectures for near-threshold computing based on multi-core clusters is a promising approach to improve the performance of smart sensing systems. In our work, we exploited a novel computing platform embedding a Parallel Ultra Low Power processor (PULP), called \u201cMr. Wolf,\u201d for the implementation of Machine Learning (ML) algorithms for touch modalities classification. First, we tested the ML algorithms at the software level; for RGB images as a case study and tactile dataset, we achieved accuracy respectively equal to 97% and 83.5%. After validating the effectiveness of the ML algorithm at the software level, we performed the on-board classification of two touch modalities, demonstrating the promising use of Mr. Wolf for smart sensing systems. Moreover, we proposed a memory management strategy for storing the needed amount of trained tensors (i.e., 50 trained tensors for each class) in the on-chip memory. We evaluated the execution cycles for Mr. Wolf using a single core, 2 cores, and 3 cores, taking advantage of the benefits of the parallelization. We presented a comparison with the popular low power ARM Cortex-M4F microcontroller employed, usually for battery-operated devices. We showed that the ML algorithm on the proposed platform runs 3.7 times faster than ARM Cortex M4F (STM32F40), consuming only 28 mW. The proposed platform achieves 15 7 better energy efficiency than the classification done on the STM32F40, consuming 81mJ per classification and 150 pJ per operation

    The tracking detector of the FASER experiment

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    Scintillator Pad Detector: Very Front End Electronics

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    El Laboratori d'Altes Energies de La Salle és un membre d'un grup acreditat per la Generalitat. Aquest grup està format per part del Departament d'Estructura i Constituents de la Matèria de la Facultat de Física de la Universitat de Barcelona, part del departament d'Electrònica de la mateixa Facultat i pel grup de La Salle. Tots ells estan involucrats en el disseny d'un subdetector en l'experiment de LHCb del CERN: el SPD (Scintillator Pad Detector). El SPD és part del Calorímetre de LHCb. Aquest sistema proporciona possibles hadrons d'alta energia, electrons i fotons pel primer nivell de trigger. El SPD està format per una làmina centellejeadora de plàstic, dividida en 600 cel.les de diferent tamany per obtenir una millor granularitat aprop del feix. Les partícules carregades que travessin el centellejador generaran una ionització del mateix, a diferència dels fotons que no la ionitzaran. Aquesta ionització, generarà un pols de llum que serà recollit per una WLS que està enrotllada dins de les cel.les centellejadores. La llum serà transmesa al sistema de lectura mitjançant fibres clares. Per reducció de costos, aquestes 6000 cel.les estan dividides en grups, usant MAPMT (fotomultiplicadors multiànode) de 64 canals per rebre la informació en el sistema de lectura. El senyal de sortida dels fotomultilplicadors és irregular degut al baix nivell de fotoestadística, uns 20-30 fotoelectrons per MIP, i degut també a la resposta de la fibra WLS, que té un temps de baixada lent. Degut a tot això, el processat del senyal, es realitza primer durant la integració de la càrrega total i finalment per la correcció de la cua que conté el senyal provinent del PMT. Aquesta Tesi està enfocada en el sistema de lectura de l'electrònica del VFE del SPD. Aquest, està format per un ASIC (dissenyat pel grup de la UB) encarregat d'integrar el senyal, compensar el senyal restant i comparar el nivell d'energia obtingut amb un llindar programable (fa la distinció entre electrons i fotons), una FPGA que programa aquests llindars i compensacions de cada ASIC i fa el mapeig de cada canal rebut en el detector i finalment usa serialitzadors LVDS per enviar la informació de sortida al trigger de primer nivell. En el disseny d'aquest tipus d'electrònica s'haurà de tenir en compte, per un costat, restriccions de tipus mecànic: l'espai disponible per l'electrònica és limitat i escàs, i per un altre costat, el nivell de radiació que deurà suportar és considerable i s'haurà de comprobar que tots els components superin un cert test de radiació, i finalment, també s'haurà de tenir en compte la distància que separa els VFE dels racks on la informació és enviada i el tipus de senyal amb el que es treballa en aquest tipus d'experiments: mixta i de poc rang.El Laboratorio de Altas Energías de la Salle es un miembro de un grupo acreditado por La Generalitat. Este grupo está formado por parte del departamento de Estructura i Constituents de la Matèria de la Facultad de Física de la Universidad de Barcelona, parte del departamento de Electrónica de la misma Facultad y el grupo de La Salle. Todos ellos están involucrados en el diseño de un subdetector en el experimento de LHCb del CERN: El SPD (Scintillator Pad Detector). El SPD es parte del Calorímetro de LHCb. Este sistema proporciona posibles hadrones de alta energía, electrones y fotones para el primer nivel de trigger.El SPD está diseñado para distinguir entre electrones y fotones para el trigger de primer nivel. Este detector está formado por una lámina centelleadora de plástico, dividida en 6000 celdas de diferente tamaño para obtener una mejor granularidad cerca del haz. Las partículas cargadas que atraviesen el centelleador generarán una ionización del mismo, a diferencia de los fotones que no la generarán. Esta ionización generará, a su vez, un pulso de luz que será recogido por una WLS que está enrollada dentro de las celdas centelleadoras. La luz será transmitida al sistema de lectura mediante fibras claras. Para reducción de costes, estas 6000 celdas están divididas en grupos, utilizando un MAPMT (fotomultiplicadores multiánodo) de 64 canales para recibir la información en el sistema de lectura. La señal de salida de los fotomultiplicadores es irregular debido al bajo nivel de fotoestadística, unos 20-30 fotoelectrones por MIP, y debido también a la respuesta de la fibra WLS, que tiene un tiempo de bajada lento. Debido a todo esto, el procesado de la señal, se realiza primero mediante la integración de la carga total y finalmente por la substracción de la señal restante fuera del período de integración. Esta Tesis está enfocada en el sistema de lectura de la electrónica del VFE del SPD. Éste, está formado por un ASIC (diseñado por el grupo de la UB) encargado de integrar la señal, compensar la señal restante y comparar el nivel de energía obtenido con un umbral programable (que distingue entre electrones y fotones), y una FPGA que programa estos umbrales y compensaciones de cada ASIC, y mapea cada uno de los canales recibidos en el detector y finalmente usa serializadores LVDS para enviar la información de salida al trigger de primer nivel. En el diseño de este tipo de electrónica se deberá tener en cuenta, por un lado, restricciones del tipo mecánico: el espacio disponible para la electrónica en sí, es limitado y escaso, por otro lado, el nivel de radiación que deberá soportar es considerable y se tendrá que comprobar que todos los componentes usado superen un cierto test de radiación, y finalmente, también se deberá tener en cuenta la distancia que separa los VFE de los racks dónde la información es enviada y el tipo de señal con el que se trabaja en este tipo de experimentos: mixta y de poco rango.Laboratory in La Salle is a member of a Credited Research Group by La Generatitat. This group is formed by a part of the ECM department, a part of the Electronics department at UB (University of Barcelona) and La Salle's group. Together, they are involved in the design of a subdetector at LHCb Experiment at CERN: the SPD (Scintillator Pad Detector). The SPD is a part of LHCb Calorimeter. That system provides high energy hadrons, electron and photons candidates for the first level trigger. The SPD is designed to distinguish electrons and photons for this first level trigger. This detector is a plastic scintillator layer, divided in about 6000 cells of different size to obtain better granularity near the beam. Charged particles will produce, and photons will not, ionisation on the scintillator. This ionisation generates a light pulse that is collected by a Wavelength Shifting (WLS) fibre that is twisted inside the scintillator cell. The light is transmitted through a clear fibre to the readout system. For cost reduction, these 6000 cells are divided in groups using a MAPMT of 64 channels for receiving information in the readout system. The signal outing the SPD PMTs is rather unpredictable as a result of the low number of photostatistics, 20-30 photoelectrons per MIP, and the due to the response of the WLS fibre, which has low decay time. Then, the signal processing must be performed by first integrating the total charge and later subtracting to avoid pile-up. This PhD is focused on the VFE (Very Front End) of SPD Readout system. It is performed by a specific ASIC (designed by the UB group) which integrates the signal, makes the pile-up compensation, and compares the level obtained to a programmable threshold (distinguishing electrons and photons), an FPGA which programs the ASIC thresholds, pile-up subtraction and mapping the channels in the detector and finally LVDS serializers, in order to send information to the first level trigger system. Not only mechanical constraints had to be taken into account in the design of the card as a result of the little space for the readout electronics but also, on one hand, the radiation quote expected in the environment and on the other hand, the distance between the VFE electronics and the racks were information is sent and the signal range that this kind of experiments usually have

    HiRes camera and lidar ranging system for the Clementine mission

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    Embedded electronic systems driven by run-time reconfigurable hardware

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    Abstract This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology –available through SRAM-based FPGA/SoC devices– aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation –silicon area, processing time, complexity, flexibility, functional density, cost and power consumption– in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen Esta tesis doctoral abarca el diseño de sistemas electrónicos embebidos basados en tecnología hardware dinámicamente reconfigurable –disponible a través de dispositivos lógicos programables SRAM FPGA/SoC– que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguración que proporcione a la FPGA la capacidad de reconfiguración dinámica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicación particionada en tareas multiplexadas en tiempo y en espacio, optimizando así su implementación física –área de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipada– comparada con otras alternativas basadas en hardware estático (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalúa el flujo de diseño de dicha tecnología a través del prototipado de varias aplicaciones de ingeniería (sistemas de control, coprocesadores aritméticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotación en la industria.Resum Aquesta tesi doctoral està orientada al disseny de sistemes electrònics empotrats basats en tecnologia hardware dinàmicament reconfigurable –disponible mitjançant dispositius lògics programables SRAM FPGA/SoC– que contribueixin a la millora de la qualitat de vida de la societat. S’investiga l’arquitectura del sistema i del motor de reconfiguració que proporcioni a la FPGA la capacitat de reconfiguració dinàmica parcial dels seus recursos programables, amb l’objectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicació particionada en tasques multiplexades en temps i en espai, optimizant així la seva implementació física –àrea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potència dissipada– comparada amb altres alternatives basades en hardware estàtic (MCU, DSP, GPU, ASSP, ASIC, etc.). S’evalúa el fluxe de disseny d’aquesta tecnologia a través del prototipat de varies aplicacions d’enginyeria (sistemes de control, coprocessadors aritmètics, processadors d’imatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotació a la indústria

    Propeller design optimization for tunnel bow thrusters in the bollard pull condition

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    Thesis (Nav. E. and S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 50-51).Tunnel bow thrusters are often used by large ships to provide low-speed lateral maneuverability when docking. Required to provide high thrust while essentially at a standstill, the design point for these thrusters is the bollard pull condition. Traditionally, the term bollard pull refers to the amount of force a tug can apply to a bollard when secured to a pier. Here, the bollard pull condition is used to describe a propeller with no flow over it except for that induced by its own rotation. Conventional propeller design is primarily performed for an optimal vessel speed or range of speeds. OpenProp, a propeller design code based on lifting line theory, is a numerical model capable of design and analysis of such propellers. It has been experimentally validated for standard design conditions in an external flow, but until now has been incapable of design with no external fluid velocity component applied. Recent updates to the model now allow for bollard pull design work. This project is the first application of the OpenProp model update. Propellers are designed for both open water and ducted (tunnel) applications in OpenProp. Propeller geometry design refinement by coupling MTFLOW, an Euler Equation viscous flow solver, with PBD-14, a lifting surface design program for marine propulsors is examined. An experimental apparatus is constructed to test the propeller designs and validate the OpenProp model. A range of off-design operating conditions are analyzed and results are presented.by James R. Wilkins, IV.Nav.E.and S.M
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