Predicting the Transfer Efficiency of Stencil Printing by Machine Learning Technique

Experiment was carried out for acquiring data regarding the transfer efficiency of stencil printing, and a machine learning-based technique (artificial neural network) was trained for predicting that parameter. The input parameters space in the experiment included the printing speed at five different levels (between 20 and120 mm/s) and the area ratio of stencil apertures from 0.34 to1.69. Three types of lead-free solder paste were also investigated as follows: Type-3 (particle size range is 20–45 μm), Type-4 (20–38 μm), Type-5 (10–25 μm). The output parameter space included the height and the area of the print deposits and the respective transfer efficiency, which is the ratio of the deposited paste volume to the aperture volume. Finally, an artificial neural network was trained with the empirical data using the Levenberg–Marquardt training algorithm. The optimal tuning factor for the fine-tuning of the network size was found to be approximately 9, resulting in a hidden neuron number of 160. The trained network was able to predict the output parameters with a mean average percentage error (MAPE) lower than 3%. Though, the prediction error depended on the values of the input parameters, which is elaborated in the paper in details. The research proved the applicability of machine learning techniques in the yield prediction of the process of stencil printing

Complex low volume electronics simulation tool to improve yield and reliability

Assembly of Printed Circuit Boards (PCB) in low volumes and a high-mix requires a level of manual intervention during product manufacture, which leads to poor first time yield and increased production costs. Failures at the component-level and failures that stem from non-component causes (i.e. system-level), such as defects in design and manufacturing, can account for this poor yield. These factors have not been incorporated in prediction models due to the fact that systemfailure causes are not driven by well-characterised deterministic processes. A simulation and analysis support tool being developed that is based on a suite of interacting modular components with well defined functionalities and interfaces is presented in this paper. The CLOVES (Complex Low Volume Electronics Simulation) tool enables the characterisation and dynamic simulation of complete design; manufacturing and business processes (throughout the entire product life cycle) in terms of their propensity to create defects that could cause product failure. Details of this system and how it is being developed to fulfill changing business needs is presented in this paper. Using historical data and knowledge of previous printed circuit assemblies (PCA) design specifications and manufacturing experiences, defect and yield results can be effectively stored and re-applied for future problem solving. For example, past PCA design specifications can be used at design stage to amend designs or define process options to optimise the product yield and service reliability

Introduction to Surface-Mount Technology

In chapter 1, the surface-mount technology and reflow soldering technology are overviewed. A brief introduction is presented into the type of electronic components, including through-hole- and surface-mounted ones. Steps of reflow soldering technology are outlined, and details are given regarding the properties of solder material in this technology. The rheological behavior of solder pastes is detailed, and some recent advancements in addressing the thixotropic behavior of this material are summarized. The process of stencil printing is detailed next, which is the most crucial step in reflow soldering technology; since even 60–70% of the soldering failures can be traced back to this process. The topic includes the structures of stencils, discussion of the primary process parameters, and process optimization possibilities by numerical modeling. Process issues of component placement are presented. The critical parameter (process and machines capability), which is used extensively for characterizing the placement process is studied. In connection with the measurement of process capability, the method of Gage R&R (repeatability and reproducibility) is detailed, including the estimation of respective variances. Process of the reflow soldering itself is detailed, including the two main phenomena taking place when the solder is in the molten state, namely: wetting of the liquid solder due to surface tension, and intermetallic compound formation due to diffusion. Solder profile calculation and component movements during the soldering (e.g., self-alignment of passive components) are presented too. Lastly, the pin-in-paste technology (reflow solder of through-hole components) is detailed, including some recent advancements in the optimization of this technology by utilizing machine learning techniques

Combining business process and failure modelling to increase yield in electronics manufacturing

The prediction and capturing of defects in low-volume assembly of electronics is a technical challenge that is a prerequisite for design for manufacturing (DfM) and business process improvement (BPI) to increase first-time yields and reduce production costs. Failures at the component-level (component defects) and system-level (such as defects in design and manufacturing) have not been incorporated in combined prediction models. BPI efforts should have predictive capability while supporting flexible production and changes in business models. This research was aimed at the integration of enterprise modelling (EM) and failure models (FM) to support business decision making by predicting system-level defects. An enhanced business modelling approach which provides a set of accessible failure models at a given business process level is presented in this article. This model-driven approach allows the evaluation of product and process performance and hence feedback to design and manufacturing activities hence improving first-time yield and product quality. A case in low-volume, high-complexity electronics assembly industry shows how the approach leverages standard modelling techniques and facilitates the understanding of the causes of poor manufacturing performance using a set of surface mount technology (SMT) process failure models. A prototype application tool was developed and tested in a collaborator site to evaluate the integration of business process models with the execution entities, such as software tools, business database, and simulation engines. The proposed concept was tested for the defect data collection and prediction in the described case study

Complex Low Volume Electronics Simulation Tool to Improve Yield and Reliability

Assembly of Printed Circuit Boards (PCB) in low volumes and a high-mix requires a level of manual intervention during product manufacture, which leads to poor first time yield and increased production costs. Failures at the component-level and failures that stem from non-component causes (i.e. system-level), such as defects in design and manufacturing, can account for this poor yield. These factors have not been incorporated in prediction models due to the fact that systemfailure causes are not driven by well-characterised deterministic processes. A simulation and analysis support tool being developed that is based on a suite of interacting modular components with well defined functionalities and interfaces is presented in this paper. The CLOVES (Complex Low Volume Electronics Simulation) tool enables the characterisation and dynamic simulation of complete design; manufacturing and business processes (throughout the entire product life cycle) in terms of their propensity to create defects that could cause product failure. Details of this system and how it is being developed to fulfill changing business needs is presented in this paper. Using historical data and knowledge of previous printed circuit assemblies (PCA) design specifications and manufacturing experiences, defect and yield results can be effectively stored and re-applied for future problem solving. For example, past PCA design specifications can be used at design stage to amend designs or define process options to optimise the product yield and service reliability

Effects of Solder Paste Volume on PCBA Assembly Yield and Reliability

Solder paste printing is the most common method for attaching surface mount devices to printed circuit boards and it has been reported that a majority of all assembly defects occur during the stencil printing process. It is also recognized that the solder paste printing process is wholly responsible for the solder joint formation of leadless package technologies such as Land Grid Array (LGA) and Quad-Flat No-Lead (QFN) components and therefore is a determining factor in the long-term reliability of said devices. The goal of this experiment is to determine the acceptable lower limit for solder paste volume deposit tolerances during stencil printing process to ensure both good assembly yield and reliability expectations. Stencils with modified aperture dimensions at particular locations for LGA and QFN package footprints were designed in order to vary the solder paste volume deposited during the stencil printing process. Solder paste volumes were measured using Solder Paste Inspection (SPI) system. Low volume solder paste deposits were generated using the modified stencil designs to evaluate assemble yield. Accelerated Thermal Cycling (ATC) was used to determine the reliability of the solder joints. For the LGAs, solder joints formed with higher paste volume survived longer in ATC compared to lower volume joints. Low solder paste volume deposits did not affect BGA devices in ATC. Transfer efficiency numbers for both good assembly yield and good reliability are reported for LGA, QFN and BGA devices. This research provides valuable data because, very little data is available on solder paste volume tolerance limits in terms of assembly yield and reliability. Manufacturers often use ±50% of stencil aperture volume with no evidence of its effectiveness in determining yield and reliability of the solder joints

A Hierarchical, Fuzzy Inference Approach to Data Filtration and Feature Prioritization in the Connected Manufacturing Enterprise

The current big data landscape is one such that the technology and capability to capture and storage of data has preceded and outpaced the corresponding capability to analyze and interpret it. This has led naturally to the development of elegant and powerful algorithms for data mining, machine learning, and artificial intelligence to harness the potential of the big data environment. A competing reality, however, is that limitations exist in how and to what extent human beings can process complex information. The convergence of these realities is a tension between the technical sophistication or elegance of a solution and its transparency or interpretability by the human data scientist or decision maker. This dissertation, contextualized in the connected manufacturing enterprise, presents an original Fuzzy Approach to Feature Reduction and Prioritization (FAFRAP) approach that is designed to assist the data scientist in filtering and prioritizing data for inclusion in supervised machine learning models. A set of sequential filters reduces the initial set of independent variables, and a fuzzy inference system outputs a crisp numeric value associated with each feature to rank order and prioritize for inclusion in model training. Additionally, the fuzzy inference system outputs a descriptive label to assist in the interpretation of the feature’s usefulness with respect to the problem of interest. Model testing is performed using three publicly available datasets from an online machine learning data repository and later applied to a case study in electronic assembly manufacture. Consistency of model results is experimentally verified using Fisher’s Exact Test, and results of filtered models are compared to results obtained by the unfiltered sets of features using a proposed novel metric of performance-size ratio (PSR)