Low-power switched capacitor voltage reference

Low-power analog design represents a developing technological trend as it emerges from a rather limited range of applications to a much wider arena affecting mainstream market segments. It especially affects portable electronics with respect to battery life, performance, and physical size. Meanwhile, low-power analog design enables technologies such as sensor networks and RFID. Research opportunities abound to exploit the potential of low power analog design, apply low-power to established fields, and explore new applications. The goal of this effort is to design a low-power reference circuit that delivers an accurate reference with very minimal power consumption. The circuit and device level low-power design techniques are suitable for a wide range of applications. To meet this goal, switched capacitor bandgap architecture was chosen. It is the most suitable for developing a systematic, and groundup, low-power design approach. In addition, the low-power analog cell library developed would facilitate building a more complex low-power system. A low-power switched capacitor bandgap was designed, fabricated, and fully tested. The bandgap generates a stable 0.6-V reference voltage, in both the discrete-time and continuous-time domain. The system was thoroughly tested and individual building blocks were characterized. The reference voltage is temperature stable, with less than a 100 ppm/°C drift, over a --60 dB power supply rejection, and below a 1 [Mu]A total supply current (excluding optional track-and-hold). Besides using it as a voltage reference, potential applications are also described using derivatives of this switched capacitor bandgap, specifically supply supervisory and on-chip thermal regulation

Variability-aware design of CMOS nanopower reference circuits

Questo lavoro è inserito nell'ambito della progettazione di circuiti microelettronici analogici con l'uso di tecnologie scalate, per le quali ha sempre maggiore importanza il problema della sensibilità delle grandezze alle variazioni di processo. Viene affrontata la progettazione di generatori di quantità di riferimento molto precisi, basati sull’uso di dispositivi che sono disponibili anche in tecnologie CMOS standard e che sono “intrinsecamente” più robusti rispetto alle variazioni di processo. Questo ha permesso di ottenere una bassa sensibilità al processo insieme ad un consumo di potenza estremamente ridotto, con il principale svantaggio di una elevata occupazione di area. Tutti i risultati sono stati ottenuti in una tecnologia 0.18μm CMOS. In particolare, abbiamo progettato un riferimento di tensione, ottenendo una deviazione standard relativa della tensione di riferimento dello 0.18% e un consumo di potenza inferiore a 70 nW, sulla base di misure su un set di 20 campioni di un singolo batch. Sono anche disponibili risultati relativi alla variabilità inter batch, che mostrano una deviazione standard relativa cumulativa della tensione di riferimento dello 0.35%. Abbiamo quindi progettato un riferimento di corrente, ottenendo anche in questo caso una sensibilità al processo della corrente di riferimento dell’1.4% con un consumo di potenza inferiore a 300 nW (questi sono risultati sperimentali ottenuti dalle misure su 20 campioni di un singolo batch). I riferimenti di tensione e di corrente proposti sono stati quindi utilizzati per la progettazione di un oscillatore a rilassamento a bassa frequenza, che unisce una ridotta sensibilità al processo, inferiore al 2%, con un basso consumo di potenza, circa 300 nW, ottenuto sulla base di simulazioni circuitali. Infine, nella progettazione dei blocchi sopra menzionati, abbiamo applicato un metodo per la determinazione della stabilità dei punti di riposo, basato sull’uso dei CAD standard utilizzati per la progettazione microelettronica. Questo approccio ci ha permesso di determinare la stabilità dei punti di riposo desiderati, e ci ha anche permesso di stabilire che i circuiti di start up spesso non sono necessari

An Ultra Low Power Voltage Regulator for RFID Application

An ultra low power and low voltage regulator for radio-frequency identification (RFID) passive tags is designed and optimized in this thesis. It consists of a low power sub-1V reference voltage generator with temperature and supply voltage ripple compensation, and a low-dropout voltage (LDO) regulator. The circuits are designed in CMOS 65nm technology. The total quiescent current of 63.8nA at 1.5V supply voltage has been achieved using properly sized transistors operating in the subthreshold region. With the low voltage property of transistors operating in subthreshold region the output regulated voltage can easily achieve 1V with load capacity of 50uA. Self-biased current sources are employed and optimized to eliminate the effect of supply voltage variation and to achieve a line regulation of 4.06mV/V. A PMOS pass device with small output resistance is used to reduce the load regulation to 6.57mV/50uA. By utilizing subthreshold properties, the temperature coefficient is reduced to 12.7 and 31ppm/°C for the reference voltage and regulated voltage, respectively. The circuits can operate well from -30°C to 50°C, a typical temperature range of the environment where RFID tags are widely deployed

Integrated Circuits for Programming Flash Memories in Portable Applications

Smart devices such as smart grids, smart home devices, etc. are infrastructure systems that connect the world around us more than before. These devices can communicate with each other and help us manage our environment. This concept is called the Internet of Things (IoT). Not many smart nodes exist that are both low-power and programmable. Floating-gate (FG) transistors could be used to create adaptive sensor nodes by providing programmable bias currents. FG transistors are mostly used in digital applications like Flash memories. However, FG transistors can be used in analog applications, too. Unfortunately, due to the expensive infrastructure required for programming these transistors, they have not been economical to be used in portable applications. In this work, we present low-power approaches to programming FG transistors which make them a good candidate to be employed in future wireless sensor nodes and portable systems. First, we focus on the design of low-power circuits which can be used in programming the FG transistors such as high-voltage charge pumps, low-drop-out regulators, and voltage reference cells. Then, to achieve the goal of reducing the power consumption in programmable sensor nodes and reducing the programming infrastructure, we present a method to program FG transistors using negative voltages. We also present charge-pump structures to generate the necessary negative voltages for programming in this new configuration

CMOS Integrated Circuits for RF-powered Wireless Temperature Sensor

This dissertation presents original research contributions in the form of twelve scientific publications that represent advances related to RF-to-DC converters, reference circuits (voltage, current and frequency) and temperature sensors. The primary focus of this research was to design efficient and low power CMOS-based circuit components, which are useful in various blocks of an RF-powered wireless sensor node.  The RF-to-DC converter or rectifier converts RF energy into DC energy, which is utilized by the sensor node. In the implementation of a CMOS-based RF-to-DC converter, the threshold voltage of MOS transistors mainly affects the conversion efficiency. Hence, for the first part of this research, different threshold voltage compensation schemes were developed for the rectifiers. These schemes were divided into two parts; first, the use of the MOSFET body terminal biasing technique and second, the use of an auxiliary circuit to obtain threshold voltage compensation. In addition to these schemes, the use of an alternate signaling scheme for voltage multiplier configuration of differential input RF-harvesters has also been investigated.  A known absolute value of voltage or current is the most useful for an integrated circuit. Thus, the circuit which generates the absolute value of voltage or current is cited as the voltage or current reference circuit respectively. Hence, in the second part of the research, simple, low power and moderately accurate, voltage and current reference circuits were developed for the power management unit of the sensor node. Besides voltage and current reference circuits, a frequency reference circuit was also designed. The use of the frequency reference circuit is in the digital processing and timing functions of the sensor node.  In the final part of the research, temperature sensing was selected as an application for the sensor node. Here, voltage and current based sensor cores were developed to sense the temperature. A smart temperature sensor was designed by using the voltage cores to obtain temperature information in terms of the duty-cycle. Similarly, the temperature equivalent current was converted into the frequency to obtain a temperature equivalent output signal.  All these implementations were done by using two integrated circuits which were fabricated during the year 2013-14.

Sub-1 V, 4 nA CMOS voltage references with digitally-trimmable temperature coefficient

Voltage references are fundamental to mixed signal converters which are widely used in elec- tronics. Hence there are signicant advantages in having the voltage reference operate with less power while minimizing area consumption and maintaining performance. Past designs have suered from issues related to process variations which adversely aect the temperature coe- cient of the circuit output. To compensate for these process variations, a means to modify the temperature coecient are proposed and experimentally veried with two circuit architectures. Five test chip samples implement these architectures in a 0.35 m CMOS process. Design methodologies for both architectures are presented. Design techniques include the use of a high-swing cascode to improve Line Sensitivity while minimizing additional power consumption, accounting for a well-matched layout, and the eect of leakage currents on the performance of the circuit. Layout schematics, performance gures, test methodologies and results are presented. Each circuit dissipates less than 4 nW and operates down to 0.9 V or better with Line Sensitivity and Power Supply Rejection Ratio of less than 0.15 %/V and -58 dB respectively, while consuming an area of 0.053 mm2 or less. The experimental average and median temperature coecient was less than 26 ppm/C and 22 ppm/C respectively in the 􀀀20 C to 80 C range, with the best performance being less than 8.1 ppm/C. Areas of improvement and potential areas of future research are then identied to facilitate advancement of this work

Nano-Watt Modular Integrated Circuits for Wireless Neural Interface.

In this work, a nano-watt modular neural interface circuit is proposed for ECoG neuroprosthetics. The main purposes of this work are threefold: (1) optimizing the power-performance of the neural interface circuits based on ECoG signal characteristics, (2) equipping a stimulation capability, and (3) providing a modular system solution to expand functionality. To achieve these aims, the proposed system introduces the following contributions/innovations: (1) power-noise optimization based on the ECoG signal driven analysis, (2) extreme low-power analog front-ends, (3) Manchester clock-edge modulation clock data recovery, (4) power-efficient data compression, (5) integrated stimulator with fully programmable waveform, (6) wireless signal transmission through skin, and (7) modular expandable design. Towards these challenges and contributions, three different ECoG neural interface systems, ENI-1, ENI-16, and ENI-32, have been designed, fabricated, and tested. The first ENI system(ENI-1) is a one-channel analog front-end and fabricated in a 0.25µm CMOS process with chopper stabilized pseudo open-loop preamplifier and area-efficient SAR ADC. The measured channel power, noise and area are 1.68µW at 2.5V power-supply, 1.69µVrms (NEF=2.43), and 0.0694mm^2, respectively. The fabricated IC is packaged with customized miniaturized package. In-vivo human EEG is successfully measured with the fabricated ENI-1-IC. To demonstrate a system expandability and wireless link, ENI-16 IC is fabricated in 0.25µm CMOS process and has sixteen channels with a push-pull preamplifier, asynchronous SAR ADC, and intra-skin communication(ISCOM) which is a new way of transmitting the signal through skin. The measured channel power, noise and area are 780nW, 4.26µVrms (NEF=5.2), and 2.88mm^2, respectively. With the fabricated ENI-16-IC, in-vivo epidural ECoG from monkey is successfully measured. As a closed-loop system, ENI-32 focuses on optimizing the power performance based on a bio-signal property and integrating stimulator. ENI-32 is fabricated in 0.18µm CMOS process and has thirty-two recording channels and four stimulation channels with a cyclic preamplifier, data compression, asymmetric wireless transceiver (Tx/Rx). The measured channel power, noise and area are 140nW (680nW including ISCOM), 3.26µVrms (NEF=1.6), and 5.76mm^2, respectively. The ENI-32 achieves an order of magnitude power reduction while maintaining the system performance. The proposed nano-watt ENI-32 can be the first practical wireless closed-loop solution with a practically miniaturized implantable device.PhDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/98064/1/schang_1.pd

Fully Integrated Voltage Reference Circuits

(Doktora) -- İstanbul Teknik Üniversitesi, Fen Bilimleri Enstitüsü, 2014(PhD) -- İstanbul Technical University, Institute of Science and Technology, 2014Gerilim referans devreleri, elektriksel sistemlerde diğer alt blokların çalışmaları için kararlı bir çalışma noktası üretmeleri sebebiyle veri dönüştürücüler (ADC - DAC), frekans sentezleyiciler, DC-DC ve AC-DC dönüştürücüler ve lineer regülatörler gibi pek çok elektriksel sistemin en temel yapı bloklarındandır. İdeal olarak, üretilen bu referans noktası, sıcaklık, üretim süreçleri, besleme gerilim degişimleri ve yükleme etkileri gibi çalışma koşullarından etkilenmemelidir. Bir referans devresinin doğruluğu bahsedilen çalışma koşullarının etkisiyle mutlak değerinden ne kadar saptığı olarak tanımlanır. Modern haberleşme sistemleri ve tüketici ürünlerindeki gelişmeler ile birlikte yüksek entegrasyon ve doğruluklu sistemlere olan talep artmıştır. Tümdevre sistemlerinde, alt blokların çalışma noktalarını belirlemesi nedeniyle özellikle referans devrelerinin performansları bütün sistemin performansının belirlenmesinde önemli rol oynamaktadır. Dolayısıyla yüksek performanslı sistemlere olan talep, bu performansların elde edilmesi için kullanılan düşük geometrili üretim teknolojilerine uygun, yani giderek azalan besleme gerilimleri ile çalışabilecek yüksek doğruluklu referans devrelerine olan talebi de arttırmıştır. Bu nedenle bu çalışmada gerilim referans devre topolojilerine odaklanılmıştır. Bu doğrultuda, öncelikle yüksek doğruluklu, düşük gürültülü gerilim refereans devre topolojileri üzerinde çalışılarak 0.35 um CMOS teknoljisinde farklı tasarımlar yapılmıştır. Bu aşamada temel hedef, yüksek dogrulukluk olarak belirenmiş ve yapılan tasarımlarda, üretim sonrası ayarlamalardan sonra sıcaklık katsayısı 3 ppm/C olabilecek devreler tasarlanmıştır. Ancak, 0.35 um CMOS üretim teknolojisi kullanılması ve kullanılan topolojiler dolayısıyla, devrelerin çalışabileceği minimum besleme gerilim seviyesi 1.8 V ile sınırlı kalmıştır. Devrelerin çektikleri akımlar ise 20-30 uA seviyesindedir. Bu tasarımlar sırasında (triple-well üretim teknlojileri için), önerilen blok gövde izolasyon stratejisi, tasarımı yapılan devrenin gövdesinin tümdevrenin geri kalan kısmından ters kutuplanmış bir jonksiyon diyodu sayesinde izole edilmesine dayanmaktadır ve devrenin gövde gürültüsünden etkilenmesini önemli ölçüde azaltmaktadır. Son olarak, çoğunlukla osilatör devrelerinde uygulanan anahtarlamalı kutuplama tekniği uygulanarak devrelerin düşük frekans gürültü performansının iyileştirilmesi amaçlanmıştır. Çalışmanın geri kalan kısmında, düşük besleme gerilimleriyle çalışabilecek mikron-altı üretim teknolojilerine uygun gerilim referans devre topolojileri üzerine odaklanılmıştır. Bu doğrultuda, iki yeni düşük besleme gerilimli ve düşük güç tüketimli gerilim referans devre topolojisi önerilmiştir. Önerilen topolojiler, 0.18 um CMOS üretim teknolojisinde gerçeklenmiştir. Ölçüm sonuçları, tasarlanan gerilim refarans devrelerinin 0.65 V besleme gerilimi ile çalışabildiğini göstermiştir. Önerilen devre topolojileri ile 0-120 C sıcaklık aralığında, sıcaklık katsayısı 50 ppm/C olan 193 mV seviyesinde referans gerilimleri elde edilmiştir. Devrelerin güç tüketimleri sırasıyla 0.3 uW ve 0.4 uW iken kapladıkları alan 0.2 mm^2 ve 0.08 mm^2 dir. Sonuç olarak, önerilen devre topolojileri ile literatürde yer alan diğer 1V-altı referans devreleri ile karşılatrılabilir seviyede sıcaklık katsayısı olan referans gerilimleri çok daha düşük güç harcamasıyla elde edilmiştir.Voltage references are one of the basic building blocks of many SoCs and mixed-signal ICs such as data converters, voltage regulators and operational amplifiers as they constitute a stable reference voltage for other sub-circuits to generate predictable and repeatable results. Ideally, this reference point should not change with external influences or operating conditions such as temperature, fabrication process variations, power supply variations and transient loading effects. Along with the rapid development of modern communication systems and consumer products, which constitutes the main market for semiconductor industry, the market demand for these System on Chip (SoC) or Mixed Signal ICs to have lower power consumption, higher accuracy and lower cost, and thus, higher integration. Since the performance of the whole system depends strongly to the performance of the reference circuit, this work is focused on fully integrated voltage reference architectures. With this motivation, firstly, different kinds of high precision low noise voltage reference circuits are designed in standard 0.35 um CMOS technology that we have more experience and knowledge of. The essential goal of these studies was high precision and temperature coefficient of the designed voltage reference circuits are on the order of 3 ppm/C with trimming after production. However, since 0.35 um CMOS technology is used in these designs and also due to the chosen topologies their minimum supply voltage can be down to 1.8 V and while current consumption is on the order of 20-30 uA. In the design of the this voltage reference block bulk isolation technique is proposed (for triple-well CMOS processes), in which system blocks are bulk isolated by a reverse biased junction diode from the rest of the die to drastically reduce substrate noise coupling. This is especially important if a very low power voltage reference is designed in a very noisy SoC. Moreover, the switched biasing technique, which is mostly applied to the oscillators, is also implemented to the designed BGR in order to improve the low noise performance of the circuit. The rest of the thesis is focused on new voltage reference topologies that are appropriate for sub-micron technologies operating with low supply voltages. With this motivation two new low voltage and low power voltage reference topologies are proposed. The proposed voltage reference topologies are implemented and fabricated in 0.18 um CMOS technology. Measurement results show that the proposed voltage reference circuits are working properly down to 0.65 V and achieve an output voltage of 193 mV with a temperature coefficient on the order of 50 ppm/C in the temperature range of 0-120C. The total power consumption of the two designed voltage references are 0.3 uW and 0.4 uW at 27 C, while occupying the area of 0.2 mm^2 and 0.08 mm^2, respectively. As a result, the proposed voltage reference topologies generate a reference voltage with comparable level of temperature coefficient and quite low power consumption with respect to the other sub-1V voltage reference circuits reported in the literature.DoktoraPh