Baseband analog front-end and digital back-end for reconfigurable multi-standard terminals

Multimedia applications are driving wireless network operators to add high-speed data services such as Edge (E-GPRS), WCDMA (UMTS) and WLAN (IEEE 802.11a,b,g) to the existing GSM network. This creates the need for multi-mode cellular handsets that support a wide range of communication standards, each with a different RF frequency, signal bandwidth, modulation scheme etc. This in turn generates several design challenges for the analog and digital building blocks of the physical layer. In addition to the above-mentioned protocols, mobile devices often include Bluetooth, GPS, FM-radio and TV services that can work concurrently with data and voice communication. Multi-mode, multi-band, and multi-standard mobile terminals must satisfy all these different requirements. Sharing and/or switching transceiver building blocks in these handsets is mandatory in order to extend battery life and/or reduce cost. Only adaptive circuits that are able to reconfigure themselves within the handover time can meet the design requirements of a single receiver or transmitter covering all the different standards while ensuring seamless inter-interoperability. This paper presents analog and digital base-band circuits that are able to support GSM (with Edge), WCDMA (UMTS), WLAN and Bluetooth using reconfigurable building blocks. The blocks can trade off power consumption for performance on the fly, depending on the standard to be supported and the required QoS (Quality of Service) leve

Multirate cascaded discrete-time low-pass ΔΣ modulator for GSM/Bluetooth/UMTS

This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasing it appropriately in the second stage. Furthermore, a cascaded ΔΣ modulator enables the power efficient implementation of multiple communication standards.@The advantages of multirate cascaded ΔΣ modulators are demonstrated by comparing the performance of single-rate and multirate implementations using behavioral-level and circuit-level simulations. This analysis has been further validated with the design of a multirate cascaded triple-mode discrete-time ΔΣ modulator. A 2-1 multirate low-pass cascade, with a sampling frequency of 80 MHz in the first stage and 320 MHz in the second stage, meets the requirements for UMTS. The first stage alone is suitable for digitizing Bluetooth and GSM with a sampling frequency of 90 and 50 MHz respectively. This multimode ΔΣ modulator is implemented in a 1.2 V 90 nm CMOS technology with a core area of 0.076 mm2. Measurement results show a dynamic range of 66/77/85 dB for UMTS/ Bluetooth/GSM with a power consumption of 6.8/3.7/3.4 mW. This results in an energy per conversion step of 1.2/0.74/2.86 pJ

Design Considerations for Multistandard Cascade ΣΔ Modulators

This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.This work has been supported by the Spanish Ministry of Science and Education (with support from the European Regional Development Fund) under contract TEC2004-01752/MIC.Peer reviewe

Design Considerations for Multistandard Cascade ΣΔ Modulators

This paper discusses design considerations for cascade Sigma-Delta Modulators (ΣΔMs) included in multistandard wireless receivers. Four different standards are covered: GSM, Bluetooth, UMTS, and WLAN. A top-down design methodology is proposed to find out the optimum modulator architecture in terms of circuit complexity and reconfiguration parameters. Several reconfiguration strategies are adopted at both architecture- and circuit-level in order to adapt the modulator performance to the different standards requirements with adaptive power consumption. Time-domain behavioural simulations considering a 0.13μm CMOS implementation are shown to validate the presented approach.Ministerio de Educación y Ciencia TEC2004-01752/MI

Design of a 130-nm CMOS Reconfigurable Cascade ΣΔ Modulator for GSM/UMTS/Bluetooth

This paper reports a 130-nm CMOS programmable cascade ΣΔ modulator for multistandard wireless terminals, covering three standards: GSM, Bluetooth and UMTS. The modulator is reconfigured at both architecture- and circuitlevel in order to adapt its performance to the different standard specifications with optimized power consumption. The design of the building blocks is based upon a top-down CAD methodology that combines simulation and statistical optimization at different levels of the system hierarchy. Transistor-level simulations show correct operation for all standards, featuring 13-bit, 11.3-bit and 9-bit effective resolution within 200-kHz, 1-MHz and 4-MHz bandwidth, respectively.España, Ministerio de Educación y Ciencia TEC2004-01752/MI

[[alternative]]High Speed Low Power Sigma Delta Modulator Analog-to-Digital Converter for Heterogeneously Next Generation Communication System(I)

計畫編號：NSC96-2221-E032-053研究期間：200708~200807研究經費：911,000[[abstract]]本計畫專注於4G晶片組中介面轉換器的設計，由完整的系統模擬中，設計適合系統使用的積分三角調變器(Sigma Delta Modulator, SDM)式類比數位轉換器(Analog to Digital Converter, ADC)。在設計ADC時，由於未來的4G將使用在許多具行動概念的器材上，結合現有高經濟效益的GSM、WiMax、與WLAN等系統，多重系統的結合將是一個重要的應用趨勢；由於是行動通信器材，因此在設計電路時，必須審慎考量低功率消耗(Low Power)、高速度(High Speed)、與高解析度(High Resolution)等三項特點，以求達到長時間使用及降低成本的目的。在研究與設計4G所使用的ADC的過程中，我們將著重於從系統的層級來考慮及設計電路，也就是Top-Down Design的電路設計方式，使執行本計畫的研究生能建立對整體系統的設計概念，在有限的資源與成本下，精確的設計符合系統需求的電路，並期望藉著本研究計畫的執行，能對國內混合式系統IC的設計能力有所助益。 本計畫為期兩年，計畫中將發展下列兩項技術： (1) 多模切換技術之積分三角調變器。 使用SC電路時，適當的切換在不同系統下的電路架構，利用可重新配置的特性節省電路的功率消耗與成本；在最佳電流值與供應電流時間下，使消耗功率最佳化，同時保有高速操作的特色。 (2) 低功率消耗、高解析度的連續時間式多級串接積分三角調變器。 利用連續型積分三角調變器高速度低功率消耗的特色，使第一年完成的離散型積分三角調變器高解析度的轉換成連續型積分三角調變器，再配合最佳化功率技術，使得調變器之消耗功率達到最低，並同時保有高速度與高解析度的特色。 預期之工作項目如下： 第ㄧ年 (1) 瞭解整個4G系統，並訂定規格與參數。 (2) 以Matlab做DT MASH SDM ADC的系統參數設計。 (3) 協調各區塊信號之傳輸形式。 (4) 類比數位轉換器之參數量測及規格制定。 (5) 發展可重新配置式電路技術。 (6) 發展低功率電路技術。 (7) 高速、低功率之寬頻類比數位轉換器研製與晶片量測。 第二年 (1) 瞭解整個4G系統，並訂定規格與參數。 (2) 以Matlab做CT MASH SDM ADC的系統參數設計。 (3) 協調各區塊信號之傳輸形式。 (4) 發展CT電路。 (5) 發展低功率電路技術。 (6) 類比數位轉換器之參數量測及規格制定。 (7) 高速、低功率之寬頻類比數位轉換器研製與晶片量測。[[sponsorship]]行政院國家科學委員

Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

In wireless communication industry, the convergence of stand-alone, single application transceiver IC’s into scalable, programmable and platform based transceiver ICs, has led to the possibility to create sophisticated mobile devices within a limited volume. These multi-standard (multi-mode), MIMO, SDR and cognitive radios, ask for more adaptability and flexibility on every abstraction level of the transceiver. The adaptability and flexibility of the receive paths require a digitized receiver architecture in which most of the adaptability and flexibility is shifted in the digital domain. This trend to ask for more adaptability and flexibility, but also more performance, higher efficiency and an increasing functionality per volume, has a major impact on the IP blocks such systems are built with. At the same time the increasing requirement for more digital processing in the same volume and for the same power has led to mainstream CMOS feature size scaling, leading to smaller, faster and more efficient transistors, optimized to increase processing efficiency per volume (smaller area, lower power consumption, faster digital processing). As wireless receivers is a comparably small market compared to digital processors, the receivers also have to be designed in a digitally optimized technology, as the processor and transceiver are on the same chip to reduce device volume. This asks for a generalized approach, which maps application requirements of complex systems (such as wireless receivers) on the advantages these digitally optimized technologies bring. First, the application trends are gathered in five quality indicators being: (algorithmic) accuracy, robustness, flexibility, efficiency, and emission, of which the last one is not further analyzed in this thesis. Secondly, using the quality indicators, it is identified that by introducing (or increasing) digitization at every abstraction level of a system, the advantages of modern digitally optimized technologies can be exploited. For a system on a chip, these abstraction levels are: system/application level, analog IP architecture level, circuit topology level and layout level. In this thesis, the quality indicators together with the digitization at different abstraction levels are applied to S¿ modulators. S¿ modulator performance properties are categorized into the proposed quality indicators. Next, it is identified what determines the accuracy, robustness, flexibility and efficiency of a S¿ modulator. Important modulator performance parameters, design parameter relations, and performance-cost relations are derived. Finally, several implementations are presented, which are designed using the found relations. At least one implementation example is shown for each level of digitization. At system level, a flexible (N)ZIF receiver architecture is digitized by shifting the ADC closer to the antenna, reducing the amount of analog signal conditioning required in front of the ADC, and shifting the re-configurability of such a receiver into the digital domain as much as possible. Being closer to the antenna, and because of the increased receiver flexibility, a high performance, multi-mode ADC is required. In this thesis, it is proven that such multi-mode ADCs can be made at low area and power consumption. At analog IP architecture level, a smarter S¿ modulator architecture is found, which combines the advantages of 1-bit and multi-bit modulators. The analog loop filter is partly digitized, and analog circuit blocks are replaced by a digital filter, leading to an area and power efficient design, which above all is very portable, and has the potential to become a good candidate for the ADC in multimode receivers. At circuit and layout level, analog circuits are designed in the same way as digital circuits are. Analog IP blocks are split up in analog unit cells, which are put in a library. For each analog unit cell, a p-cell layout view is created. Once such a library is available, different IP blocks can be created using the same unit cells and using the automatic routing tools normally used for digital circuits. The library of unit cells can be ported to a next technology very quickly, as the unit cells are very simple circuits, increasing portability of IP blocks made with these unit cells. In this thesis, several modulators are presented that are designed using this digital design methodology. A high clock frequency in the giga-hertz range is used to test technology speed. The presented modulators have a small area and low power consumption. A modulator is ported from a 65nm to a 45nm technology in one month without making changes to the unit cells, or IP architecture, proving that this design methodology leads to very portable designs. The generalized system property categorization in quality indicators, and the digitization at different levels of system design, is named the digital design methodology. In this thesis this methodology is successfully applied to S¿ modulators, leading to high quality, mixed-signal S¿ modulator IP, which is more accurate, more robust, more flexible and/or more efficient

Multi-Standard Mobile Terminals

ABSTRACT This paper presents an investigation of a radio receiver architecture to enable multi-standard (GPRS, WCDMA, HiperLAN2) implementation in mobile terminals. The architecture uses partial radio band digitisation at an intermediate frequency. Following circuit progress and industry trends (e.g. Moore's law) we estimate components for the proposed architecture with acceptable power consumption to be available within the next 5 years

A ΔΣ Modulator Automated Synthesis Tool for Wireless Standards

This paper presents the prediction of single-bit discrete-time feed-forward Delta-Sigma (DT FF ΔΣ) modulators performance for wireless standards with the use of two methods. The presented work uses the MAPLE tool and a new design automation tool to estimate the performance of different DT FF ΔΣ modulators topologies intended for low power consumption systems. The proposed tool is based on synthesis algorithm, which takes advantage of analytical models of both FF ΔΣ modulator and operational transconductance amplifier (OTA) performance. By defining the required specifications, the proposed synthesis tool is capable to find the predictive performance of both the modulator topology and the required OTA building block for future process. A Graphical User Interface is programmed to easily present some designed circuits examples

Resonation-based hybrid continuous-time/discrete-time cascade ΣΔ modulators: application to 4G wireless telecom

This paper presents innovative architectures of hybrid Continuous-Time/Discrete-Time (CT/DT) cascade ΣΔ Modulators (ΣΔMs) made up of a front-end CT stage and a back-end DT stage. In addition to increasing the digitized signal bandwidth as compared to conventional ΣΔMs, the proposed topologies take advantage of the CT nature of the front-end ΣΔM stage, by embedding anti-aliasing filtering as well as their suitability to operate up to the GHz range. Moreover, the presented modulators include multi-bit quantization and Unity Signal Transfer Function (USTF) in both stages to reduce the integrator output swings, and programmable resonation to optimally distribute the zeroes of the overall Noise Transfer Function (NTF), such that the in-band quantization noise is minimized for each operation mode. Both local and inter-stage (global) based resonation architectures are synthesized and compared in terms of their circuit complexity, resolution-bandwidth programmability and robustness with respect to circuit non-ideal effects. The combination of all mentioned characteristics results in novel hybrid ΣΔMs, very suited for the implementation of adaptive/reconfigurable Analog-to-Digital Converters (ADCs) intended for the 4th Generation (4G) of wireless telecom systems