A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Full 3D Quantum Transport Simulation of Atomistic Interface Roughness in Silicon Nanowire FETs

The influence of interface roughness scattering (IRS) on the performances of silicon nanowire field-effect transistors (NWFETs) is numerically investigated using a full 3D quantum transport simulator based on the atomistic sp3d5s* tight-binding model. The interface between the silicon and the silicon dioxide layers is generated in a real-space atomistic representation using an experimentally derived autocovariance function (ACVF). The oxide layer is modeled in the virtual crystal approximation (VCA) using fictitious SiO2 atoms. -oriented nanowires with different diameters and randomly generated surface configurations are studied. The experimentally observed ON-current and the threshold voltage is quantitatively captured by the simulation model. The mobility reduction due to IRS is studied through a qualitative comparison of the simulation results with the experimental results

Atomistic Boron-Doped Graphene Field Effect Transistors: A Route towards Unipolar Characteristics

We report fully quantum simulations of realistic models of boron-doped graphene-based field effect transistors, including atomistic details based on DFT calculations. We show that the self-consistent solution of the three-dimensional (3D) Poisson and Schr\"odinger equations with a representation in terms of a tight-binding Hamiltonian manages to accurately reproduce the DFT results for an isolated boron-doped graphene nanoribbon. Using a 3D Poisson/Schr\"odinger solver within the Non-Equilibrium Green's Functions (NEGF) formalism, self-consistent calculations of the gate-screened scattering potentials induced by the boron impurities have been performed, allowing the theoretical exploration of the tunability of transistor characteristics. The boron-doped graphene transistors are found to approach unipolar behavior as the boron concentration is increased, and by tuning the density of chemical dopants the electron-hole transport asymmetry can be finely adjusted. Correspondingly, the onset of a mobility gap in the device is observed. Although the computed asymmetries are not sufficient to warrant proper device operation, our results represent an initial step in the direction of improved transfer characteristics and, in particular, the developed simulation strategy is a powerful new tool for modeling doped graphene nanostructures.Comment: 7 pages, 5 figures, published in ACS Nan

Advanced III-V / Si nano-scale transistors and contacts: Modeling and analysis

The exponential miniaturization of Si CMOS technology has been a key to the electronics revolution. However, the continuous downscaling of the gate length becomes the biggest challenge to maintain higher speed, lower power, and better electrostatic integrity for each following generation. Hence, novel devices and better channel materials than Si are considered to improve the metal-oxide-semiconductor field-effect transistors (MOSFETs) device performance. III-V compound semiconductors and multi-gate structures are being considered as promising candidates in the next CMOS technology. III-V and Si nano-scale transistors in different architectures are investigated (1) to compare the performance between InGaAs of III-V compound semiconductors and strained-Si in planar FETs and triple-gate non-planar FinFETs. (2) to demonstrate whether or not these technologies are viable alternatives to Si and conventional planar FETs. The simulation results indicate that III-V FETs do not outperform Si FETs in the ballistic transport regime, and triple-gate FinFETs surely represent the best architecture for sub-15nm gate contacts, independently from the choice of channel material. ^ This work also proves that the contact resistance becomes a limiting factor of device performance as it takes larger fraction of the total on-state resistance. Hence, contact resistance must be reduced to meet the next ITRS requirements. However, from a modeling point of view, the understanding of the contacts still remains limited due to its size and multiple associated scattering effects, while the intrinsic device performance can be projected. Therefore, a precise theoretical modeling is required to advance optimized contact design to improve overall device performance. In this work, various factors of the contact resistances are investigated within realistic contact-to-channel structure of III-V quantum well field-effect transistors (QWFET). The key finding is that the contact-to-channel resistance is mainly caused by structural reasons: 1) barriers between multiple layers in the contact region 2) Schottky barrier between metal and contact pad. These two barriers work as bottleneck of the system conductance. The extracted contact resistance matches with the experimental value. The approximation of contact resistance from quantum transport simulation can be very useful to guide better contact designs of the future technology nodes. ^ The theoretical modeling of these nano-scale devices demands a proper treatment of quantum effects such as the energy-level quantization caused by strong quantum confinement of electrons and band structure non-parabolicity. 2-D and 3-D quantum transport simulator that solves non-equilibrium Green\u27s functions (NEGF) transport and Poisson equations self-consistently within a real-space effective mass approximation. The sp3d5s* empirical tight-binding method is employed to include non-parabolicity to obtain more accurate effective masses in confined nano-structures. The accomplishment of this work would aid in designing, engineering and manufacturing nano-scale devices, as well as next-generation microchips and other electronics with nano-scale features