A survey of FPGA-based LDPC decoders

Low-Density Parity Check (LDPC) error correction decoders have become popular in communications systems, as a benefit of their strong error correction performance and their suitability to parallel hardware implementation. A great deal of research effort has been invested into LDPC decoder designs that exploit the flexibility, the high processing speed and the parallelism of Field-Programmable Gate Array (FPGA) devices. FPGAs are ideal for design prototyping and for the manufacturing of small-production-run devices, where their in-system programmability makes them far more cost-effective than Application-Specific Integrated Circuits (ASICs). However, the FPGA-based LDPC decoder designs published in the open literature vary greatly in terms of design choices and performance criteria, making them a challenge to compare. This paper explores the key factors involved in FPGA-based LDPC decoder design and presents an extensive review of the current literature. In-depth comparisons are drawn amongst 140 published designs (both academic and industrial) and the associated performance trade-offs are characterised, discussed and illustrated. Seven key performance characteristics are described, namely their processing throughput, latency, hardware resource requirements, error correction capability, processing energy efficiency, bandwidth efficiency and flexibility. We offer recommendations that will facilitate fairer comparisons of future designs, as well as opportunities for improving the design of FPGA-based LDPC decoder

Decoding of Decode and Forward (DF) Relay Protocol using Min-Sum Based Low Density Parity Check (LDPC) System

Decoding high complexity is a major issue to design a decode and forward (DF) relay protocol. Thus, the establishment of low complexity decoding system would beneficial to assist decode and forward relay protocol. This paper reviews existing methods for the min-sum based LDPC decoding system as the low complexity decoding system. Reference lists of chosen articles were further reviewed for associated publications. This paper introduces comprehensive system model representing and describing the methods developed for LDPC based for DF relay protocol. It is consists of a number of components: (1) encoder and modulation at the source node, (2) demodulation, decoding, encoding and modulation at relay node, and (3) demodulation and decoding at the destination node. This paper also proposes a new taxonomy for min-sum based LDPC decoding techniques, highlights some of the most important components such as data used, result performances and profiles the Variable and Check Node (VCN) operation methods that have the potential to be used in DF relay protocol. Min-sum based LDPC decoding methods have the potential to provide an objective measure the best tradeoff between low complexities decoding process and the decoding error performance, and emerge as a cost-effective solution for practical application

High throughput low power decoder architectures for low density parity check codes

A high throughput scalable decoder architecture, a tiling approach to reduce the complexity of the scalable architecture, and two low power decoding schemes have been proposed in this research. The proposed scalable design is generated from a serial architecture by scaling the combinational logic; memory partitioning and constructing a novel H matrix to make parallelization possible. The scalable architecture achieves a high throughput for higher values of the parallelization factor M. The switch logic used to route the bit nodes to the appropriate checks is an important constituent of the scalable architecture and its complexity is high with higher M. The proposed tiling approach is applied to the scalable architecture to simplify the switch logic and reduce gate complexity. The tiling approach generates patterns that are used to construct the H matrix by repeating a fixed number of those generated patterns. The advantages of the proposed approach are two-fold. First, the information stored about the H matrix is reduced by onethird. Second, the switch logic of the scalable architecture is simplified. The H matrix information is also embedded in the switch and no external memory is needed to store the H matrix. Scalable architecture and tiling approach are proposed at the architectural level of the LDPC decoder. We propose two low power decoding schemes that take advantage of the distribution of errors in the received packets. Both schemes use a hard iteration after a fixed number of soft iterations. The dynamic scheme performs X soft iterations, then a parity checker cHT that computes the number of parity checks in error. Based on cHT value, the decoder decides on performing either soft iterations or a hard iteration. The advantage of the hard iteration is so significant that the second low power scheme performs a fixed number of iterations followed by a hard iteration. To compensate the bit error rate performance, the number of soft iterations in this case is higher than that of those performed before cHT in the first scheme

Design of a simulation platform to test next generation of terrestrial DVB

Digital Terrestrial Television Broadcasting (DTTB) is a member of our daily life routine, and nonetheless, according to new users’ necessities in the fields of communications and leisure, new challenges are coming up. Moreover, the current Standard is not able to satisfy all the potential requirements. For that reason, first of all, a review of the current Standard has been performed within this work. Then, it has been identified the needing of developing a new version of the standard, ready to support enhanced services, as for example broadcasting transmissions to moving terminals or High Definition Television (HDTV) transmissions, among others. The main objective of this project is the design and development of a physical layer simulator of the whole DVB-T standard, including both the complete transmission and reception procedures. The simulator has been developed in Matlab. A detailed description of the simulator both from a functional and an architectural point of view is included. The simulator is the base for testing any possible modifications that may be included into the DVB-T2 future standard. In fact, several proposed enhancements have already been carried out and their performance has been evaluated. Specifically, the use of higher order modulation schemes, and the corresponding modifications in all the system blocks, have been included and evaluated. Furthermore, the simulator will allow testing other enhancements as the use of more efficient encoders and interleavers, MIMO technologies, and so on. A complete set of numerical results showing the performance of the different parts of the system, are presented in order to validate the correctness of the implementation and to evaluate both the current standard performance and the proposed enhancements. This work has been performed within the context of a project called FURIA, which is a strategic research project funded by the Spanish Ministry of Industry, Tourism and Commerce. A brief description of this project and its consortium has been also included herein, together with an introduction to the current situation of the DTTB in Spain (called TDT in Spanish)

새로운 소실 채널을 위한 자기동형 군 복호기 및 부분 접속 복구 부호 및 일반화된 근 프로토그래프 LDPC 부호의 설계

학위논문 (박사)-- 서울대학교 대학원 : 공과대학 전기·컴퓨터공학부, 2019. 2. 노종선.In this dissertation, three main contributions are given asi) new two-stage automorphism group decoders (AGD) for cyclic codes in the erasure channel, ii) new constructions of binary and ternary locally repairable codes (LRCs) using cyclic codes and existing LRCs, and iii) new constructions of high-rate generalized root protograph (GRP) low-density parity-check (LDPC) codes for a nonergodic block interference and partially regular (PR) LDPC codes for follower noise jamming (FNJ), are considered. First, I propose a new two-stage AGD (TS-AGD) for cyclic codes in the erasure channel. Recently, error correcting codes in the erasure channel have drawn great attention for various applications such as distributed storage systems and wireless sensor networks, but many of their decoding algorithms are not practical because they have higher decoding complexity and longer delay. Thus, the AGD for cyclic codes in the erasure channel was introduced, which has good erasure decoding performance with low decoding complexity. In this research, I propose new TS-AGDs for cyclic codes in the erasure channel by modifying the parity check matrix and introducing the preprocessing stage to the AGD scheme. The proposed TS-AGD is analyzed for the perfect codes, BCH codes, and maximum distance separable (MDS) codes. Through numerical analysis, it is shown that the proposed decoding algorithm has good erasure decoding performance with lower decoding complexity than the conventional AGD. For some cyclic codes, it is shown that the proposed TS-AGD achieves the perfect decoding in the erasure channel, that is, the same decoding performance as the maximum likelihood (ML) decoder. For MDS codes, TS-AGDs with the expanded parity check matrix and the submatrix inversion are also proposed and analyzed. Second, I propose new constructions of binary and ternary LRCs using cyclic codes and existing two LRCs for distributed storage system. For a primitive work, new constructions of binary and ternary LRCs using cyclic codes and their concatenation are proposed. Some of proposed binary LRCs with Hamming weights 4, 5, and 6 are optimal in terms of the upper bounds. In addition, the similar method of the binary case is applied to construct the ternary LRCs with good parameters. Also, new constructions of binary LRCs with large Hamming distance and disjoint repair groups are proposed. The proposed binary linear LRCs constructed by using existing binary LRCs are optimal or near-optimal in terms of the bound with disjoint repair group. Last, I propose new constructions of high-rate GRP LDPC codes for a nonergodic block interference and anti-jamming PR LDPC codes for follower jamming. The proposed high-rate GRP LDPC codes are based on nonergodic two-state binary symmetric channel with block interference and Nakagami-$m$ block fading. In these channel environments, GRP LDPC codes have good performance approaching to the theoretical limit in the channel with one block interference, where their performance is shown by the channel threshold or the channel outage probability. In the proposed design, I find base matrices using the protograph extrinsic information transfer (PEXIT) algorithm. Also, the proposed new constructions of anti-jamming partially regular LDPC codes is based on follower jamming on the frequency-hopped spread spectrum (FHSS). For a channel environment, I suppose follower jamming with random dwell time and Rayleigh block fading environment with M-ary frequnecy shift keying (MFSK) modulation. For a coding perspective, an anti-jamming LDPC codes against follower jamming are introduced. In order to optimize the jamming environment, the partially regular structure and corresponding density evolution schemes are used. A series of simulations show that the proposed codes outperforms the 802.16e standard in the presence of follower noise jamming.이 논문에서는, i) 소실 채널에서 순환 부호의 새로운 이단 자기동형 군 복호기 , ii) 분산 저장 시스템을 위한 순환 부호 및 기존의 부분 접속 복구 부호(LRC)를 이용한 이진 혹은 삼진 부분 접속 복구 부호 설계법, 및 iii) 블록 간섭 환경을 위한 고부효율의 일반화된 근 프로토그래프(generalized root protograph, GRP) LDPC 부호 및 추적 재밍 환경을 위한 항재밍 부분 균일 (anti-jamming paritally regular, AJ-PR) LDPC 부호가 연구되었다. 첫번째로, 소실 채널에서 순환 부호의 새로운 이단 자기동형 군 복호기를 제안하였다. 최근 분산 저장 시스템 혹은 무선 센서 네트워크 등의 응용으로 인해 소실 채널에서의 오류 정정 부호 기법이 주목받고 있다. 그러나 많은 복호기 알고리즘은 높은 복호 복잡도 및 긴 지연으로 인해 실용적이지 못하다. 따라서 낮은 복호 복잡도 및 높은 성능을 보일 수 있는 순환 부호에서 이단 자기 동형 군 복호기가 제안되었다. 본 연구에서는 패리티 검사 행렬을 변형하고, 전처리 과정을 도입한 새로운 이단 자기동형 군 복호기를 제안한다. 제안한 복호기는 perfect 부호, BCH 부호 및 최대 거리 분리 (maximum distance separable, MDS) 부호에 대해서 분석되었다. 수치 분석을 통해, 제안된 복호 알고리즘은 기존의 자기 동형 군 복호기보다 낮은 복잡도를 보이며, 몇몇의 순환 부호 및 소실 채널에서 최대 우도 (maximal likelihood, ML)과 같은 수준의 성능임을 보인다. MDS 부호의 경우, 확장된 패리티검사 행렬 및 작은 크기의 행렬의 역연산을 활용하였을 경우의 성능을 분석한다. 두 번째로, 분산 저장 시스템을 위한 순환 부호 및 기존의 부분 접속 복구 부호 (LRC)를 이용한 이진 혹은 삼진 부분 접속 복구 부호 설계법을 제안하였다. 초기 연구로서, 순환 부호 및 연접을 활용한 이진 및 삼진 LRC 설계 기법이 연구되었다. 최소 해밍 거리가 4,5, 혹은 6인 제안된 이진 LRC 중 일부는 상한과 비교해 보았을 때 최적 설계임을 증명하였다. 또한, 비슷한 방법을 적용하여 좋은 파라미터의 삼진 LRC를 설계할 수 있었다. 그 외에 기존의 LRC를 활용하여 큰 해밍 거리의 새로운 LRC를 설계하는 방법을 제안하였다. 제안된 LRC는 분리된 복구 군 조건에서 최적이거나 최적에 가까운 값을 보였다. 마지막으로, GRP LDPC 부호는 Nakagami-$m$ 블록 페이딩 및 블록 간섭이 있는 두 상태의 이진 대칭 채널을 기반으로 한다. 이러한 채널 환경에서 GRP LDPC 부호는 하나의 블록 간섭이 발생했을 경우, 이론적 성능에 가까운 좋은 성능을 보여준다. 이러한 이론 값은 채널 문턱값이나 채널 outage 확률을 통해 검증할 수 있다. 제안된 설계에서는, 변형된 PEXIT 알고리즘을 활용하여 기초 행렬을 설계한다. 또한 AJ-PR LDPC 부호는 주파수 도약 환경에서 발생하는 추적 재밍이 있는 환경을 기반으로 한다. 채널 환경으로 MFSK 변복조 방식의 레일리 블록 페이딩 및 무작위한 지속 시간이 있는 재밍 환경을 가정한다. 이러한 재밍 환경으로 최적화하기 위해, 부분 균일 구조 및 해당되는 밀도 진화 (density evolution, DE) 기법이 활용된다. 여러 시뮬레이션 결과는 추적 재밍이 존재하는 환경에서 제안된 부호가 802.16e에 사용되었던 LDPC 부호보다 성능이 우수함을 보여준다.Contents Abstract Contents List of Tables List of Figures 1 INTRODUCTION 1.1 Background 1.2 Overview of Dissertation 1.3 Notations 2 Preliminaries 2.1 IED and AGD for Erasure Channel 2.1.1 Iterative Erasure Decoder 2.1.1 Automorphism Group Decoder 2.2. Binary Locally Repairable Codes for Distributed Storage System 2.2.1 Bounds and Optimalities of Binary LRCs 2.2.2 Existing Optimal Constructions of Binary LRCs 2.3 Channels with Block Interference and Jamming 2.3.1 Channels with Block Interference 2.3.2 Channels with Jamming with MFSK and FHSS Environment. 3 New Two-Stage Automorphism Group Decoders for Cyclic Codes in the Erasure Channel 3.1 Some Definitions 3.2 Modification of Parity Check Matrix and Two-Stage AGD 3.2.1 Modification of the Parity Check Matrix 3.2.2 A New Two-Stage AGD 3.2.3 Analysis of Modification Criteria for the Parity Check Matrix 3.2.4 Analysis of Decoding Complexity of TS-AGD 3.2.5 Numerical Analysis for Some Cyclic Codes 3.3 Construction of Parity Check Matrix and TS-AGD for Cyclic MDS Codes 3.3.1 Modification of Parity Check Matrix for Cyclic MDS Codes . 3.3.2 Proposed TS-AGD for Cyclic MDS Codes 3.3.3 Perfect Decoding by TS-AGD with Expanded Parity Check Matrix for Cyclic MDS Codes 3.3.4 TS-AGD with Submatrix Inversion for Cyclic MDS Codes . . 4 New Constructions of Binary and Ternary LRCs Using Cyclic Codes and Existing LRCs 4.1 Constructions of Binary LRCs Using Cyclic Codes 4.2 Constructions of Linear Ternary LRCs Using Cyclic Codes 4.3 Constructions of Binary LRCs with Disjoint Repair Groups Using Existing LRCs 4.4 New Constructions of Binary Linear LRCs with d ≥ 8 Using Existing LRCs 5 New Constructions of Generalized RP LDPC Codes for Block Interference and Partially Regular LDPC Codes for Follower Jamming 5.1 Generalized RP LDPC Codes for a Nonergodic BI 5.1.1 Minimum Blockwise Hamming Weight 5.1.2 Construction of GRP LDPC Codes 5.2 Asymptotic and Numerical Analyses of GRP LDPC Codes 5.2.1 Asymptotic Analysis of LDPC Codes 5.2.2 Numerical Analysis of Finite-Length LDPC Codes 5.3 Follower Noise Jamming with Fixed Scan Speed 5.4 Anti-Jamming Partially Regular LDPC Codes for Follower Noise Jamming 5.4.1 Simplified Channel Model and Corresponding Density Evolution 5.4.2 Construction of AJ-PR-LDPC Codes Based on DE 5.5 Numerical Analysis of AJ-PR LDPC Codes 6 Conclusion Abstract (In Korean)Docto

5G無線通信における誤り訂正符号化方式の評価に関する研究

早大学位記番号:新8267早稲田大

Design of a simulation platform to test next generation of terrestrial DVB

Digital Terrestrial Television Broadcasting (DTTB) is a member of our daily life routine, and nonetheless, according to new users’ necessities in the fields of communications and leisure, new challenges are coming up. Moreover, the current Standard is not able to satisfy all the potential requirements. For that reason, first of all, a review of the current Standard has been performed within this work. Then, it has been identified the needing of developing a new version of the standard, ready to support enhanced services, as for example broadcasting transmissions to moving terminals or High Definition Television (HDTV) transmissions, among others. The main objective of this project is the design and development of a physical layer simulator of the whole DVB-T standard, including both the complete transmission and reception procedures. The simulator has been developed in Matlab. A detailed description of the simulator both from a functional and an architectural point of view is included. The simulator is the base for testing any possible modifications that may be included into the DVB-T2 future standard. In fact, several proposed enhancements have already been carried out and their performance has been evaluated. Specifically, the use of higher order modulation schemes, and the corresponding modifications in all the system blocks, have been included and evaluated. Furthermore, the simulator will allow testing other enhancements as the use of more efficient encoders and interleavers, MIMO technologies, and so on. A complete set of numerical results showing the performance of the different parts of the system, are presented in order to validate the correctness of the implementation and to evaluate both the current standard performance and the proposed enhancements. This work has been performed within the context of a project called FURIA, which is a strategic research project funded by the Spanish Ministry of Industry, Tourism and Commerce. A brief description of this project and its consortium has been also included herein, together with an introduction to the current situation of the DTTB in Spain (called TDT in Spanish)