579 research outputs found

    LOT: Logic Optimization with Testability - new transformations for logic synthesis

    Get PDF
    A new approach to optimize multilevel logic circuits is introduced. Given a multilevel circuit, the synthesis method optimizes its area while simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates as well as Reed–Muller expansions have been introduced in the synthesis of multilevel circuits. This method is augmented with transformations that specifically enhance random-pattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology not only can achieve lower area than other similar tools, but that it achieves better testability compared to available testability enhancement tools such as tstfx. Specifically for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations successfully contributed toward generating smaller circuits compared to other state-of-the-art logic optimization tools

    Developing VLSI Curricula in Electrical and Computer Engineering Department

    Get PDF
    © ASEE 2010VLSI (Very Large Scale Integrated Circuits) technology has enabled the information technology revolution which greatly changed the life style of human society. Computers, internet, cellphones, digital cameras/camcorders and many other consumer electronic products are powered by VLSI technology. In the past decades, the VLSI industry was constantly driven by the miniaturization of transistors. As governed by Moore’s law, the number of transistors in the same chip area has been doubled every 12 to 18 months. Nowadays, a typical VLSI CPU chip can contain millions to billions of transistors. As a result, the design of VLSI system is becoming more and more complex. Various EDA tools must be used to help the design of modern VLSI chips. The semiconductor and VLSI industry remain strong needs for VLSI engineers each year. In this paper, efforts in developing systematic VLSI curricula in Electrical and Computer Engineering department have been proposed. The goal of the curricula is to prepare students to satisfy the growing demands of VLSI industry as well as the higher education/research institutions. Modern VLSI design needs a thorough understanding about VLSI in device, gate, module and system levels. We developed CPEG/EE 448D: Introduction to VLSI to give students a comprehensive introduction about digital VLSI design and analysis. In this course, various EDA tools (such as Mentor Graphics tools, Cadence PSPICE, Synopsys) are used in the course projects to help students practice the VLSI design. In addition, analog and mixed signal circuit design are becoming more and more important as MEMS (Microelectromechanical Systems) and Nano devices are integrated with VLSI into Systemon-Chip (SoC) design. We developed CPEG/EE 458: Analog VLSI to introduce the analog and mixed signal VLSI design. As portable electronics (e.g. laptops, cellphones, PDAs, digital cameras) becoming more and more popular, low power VLSI circuit design is becoming a hot field. We developed CPEG/EE 548: Low Power VLSI Circuit Design to introduce various low power techniques to reduce the power consumption of VLSI circuits. Nowadays the VLSI circuits can contain billions of transistors, the testing of such complex system becoming more and more challenging. We developed CPEG/EE 549: VLSI Testing to introduce various VLSI testing strategies for modern VLSI design. In addition to the design and testing, we also developed EE 448: Microelectronic Fabrication to introduce the fabrication processes of modern VLSI circuits. With such a series of VLSI related curricula, students have an opportunity to learn comprehensive knowledge and hands-on experience about VLSI circuit design, testing, fabrication and EDA tools. Students demonstrate tremendous interests in the VLSI field, and all the VLSI courses are generally oversubscripted by students in the early stage of enrollment. Many students are also doing the VLSI graduate research and published various papers/posters in the VLSI related journals/conferences

    A Hierachical Infrastrucutre for SOC Test Management

    Get PDF
    HD2BIST - a complete hierarchical framework for BIST scheduling, data-patterns delivery, and diagnosis of complex systems - maximizes and simplifies the reuse of built-in test architectures. HD2BIST optimizes the flexibility for chip designers in planning an overall SoC test strategy by defining a test access method that provides direct virtual access to each core of the system

    Agent Based Test and Repair of Distributed Systems

    Get PDF
    This article demonstrates how to use intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (Built-In Self-Test) and BISR (Built-In Self-Repair) facilities. Agents are software modules that perform monitoring, diagnosis and repair of the faults. They form together a society whose members communicate, set goals and solve tasks. An experimental solution is presented, and future developments of the proposed approach are explore

    Online and Offline BIST in IP-Core Design

    Get PDF
    This article presents an online and offline built-in self-test architecture implemented as an SRAM intellectual-property core for telecommunication applications. The architecture combines fault-latency reduction, code-based fault detection, and architecture-based fault avoidance to meet reliability constraint

    A Self-Repairing Execution Unit for Microprogrammed Processors

    Get PDF
    Describes a processor which dynamically reconfigures its internal microcode to execute each instruction using only fault-free blocks from the execution unit. Working without redundant or spare computational blocks, this self-repair approach permits a graceful performance degradatio

    RTL Design Quality Checks for Soft IPs

    Get PDF
    Soft IPs are architectural modules which are delivered in the form of synthesizable RTL level codes written in some HDL (hardware descriptive language) like Verilog or VHDL or System Verilog. They are technology independent and offer high degree of modification flexibility. RTL is the complete abstraction of our design. Since SOC complexity is growing day by day with new technologies and requirement, it will be very much difficult to debug and fix issues after physical level. So to reduce effort and increase efficiency and accuracy it is necessary to fix most of the bugs in RTL level. Also if we are using soft IP, then our bug free IP can be used by third party. So early detection of bugs helps us not to go back to entire design and do all the process again and again. One of the important issue at RTL level of a design is the Clock Domain Crossing (CDC) problem. This is the issue which affects the performance at each and every stage of the design flow. Failure in fixing these issues at the earlier stage makes the design unreliable and design performance collapses. The main issue in real time clock designs are the metastability issue. Although we cannot check or see these issues using our simulator but we have to make preventions at RTL level. This is done by restructuring the design and adding required synchronizers. One more important area of consideration in VLSI design is power consumption. In modern low power designs low power is a key factor. So design consuming less power is preferred over design consuming more power. This decision should be made as early as possible. RTL quality check helps us on this aspect. Using different tools power estimation can be performed at RTL stage which saves lots of efforts in redesigning. This project aims at checking clock domain crossing faults at RTL stage and doing redesign of circuit to eliminate those faults. Also an effort is made to compare quality of two designs in terms of delay, power consumption and area

    Fault Tolerance in Reversible Logic Circuits and Quantum Cost Optimization

    Get PDF
    Energy dissipation is a prominent factor for the very large scale integrated circuit (VLSI). The reversible logic-based circuit was capable to compute the logic without energy dissipation. Accordingly, reversible circuits are an emerging domain of research based on the low value of energy dissipation. At nano-level design, the critical factor in the logic computing paradigm is the fault. The proposed methodology of fault coverage is powerful for testability. In this article, we target three factors such as fault tolerance, fault coverage and fault detection in the reversible KMD Gates. Our analysis provides good evidence that the minimum test vector covers the 100 % fault coverage and 50 % fault tolerance in KMD Gate. Further, we show a comparison between the quantum equivalent and controlled V and V+ gate in all the types of KMD Gates. The proposed methodology mentions that after controlled V and V+ gate based ALU, divider and Vedic multiplier have a significant reduction in quantum cost. The comparative results of designs such as Vedic multiplier, division unit and ALU are obtained and they are analyzed showing significant improvement in quantum cost
    corecore