Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance

Techniques for low power analog, digital and mixed signal CMOS integrated circuit design

With the continuously expanding of market for portable devices such as wireless communication devices, portable computers, consumer electronics and implantable medical devices, low power is becoming increasingly important in integrated circuits. The low power design can increase operation time and/or utilize a smaller size and lighter-weight battery. In this dissertation, several low power complementary metal-oxide-semiconductor (CMOS) integrated circuit design techniques are investigated. A metal-oxide-semiconductor field effect transistor (MOSFET) can be operated at a lower voltage by forward-biasing the source-substrate junction. This approach has been investigated in detail and used to designing an ultra-low power CMOS operational amplifier for operation at ± 0.4 V. The issue of CMOS latchup and noise has been investigated in detail because of the forward biasing of the substrates of MOSFETs in CMOS. With increasing forward body-bias, the leakage current increases significantly. Dynamic threshold MOSFET (DTMOS) technique is proposed to overcome the drawback which is inherent in a forward-biased MOSFET. By using the DTMOS method with the forward source-body biased MOSFET, two low-power low-voltage CMOS VLSI circuits that of a CMOS analog multiplexer and a Schmitt trigger circuits are designed. In this dissertation, an adaptive body-bias technique is proposed. Adaptive body-bias voltage is generated for several operational frequencies. Another issue, which the chip design community is facing, is the development of portable, cost effective and low power supply voltage. This dissertation proposes a new cost-effective DC/DC converter design in standard 1.5 um n-well CMOS, which adopts a delay-line controller for voltage regulation

A Novel Differential Ramp Generator Circuit with PVT Compensation Structure

Applications like counter ADC demanded accurate ramp signal with low power dissipation. This paper presents a novel approach of low power differential ramp generator with negative feedback for the compensation of the variations in process, voltage, and temperature (PVT). The derived equations of the proposed ramp generator circuit show that PVT compensation is enhanced significantly. Additionally, the circuit design and simulations were done in TSMC 0.18-μm CMOS technology. The Monte Carlo simulation results and corner analysis show that the linearity of the ramp signal is about 9-bit while power dissipation of the circuit is about 2.61μW

High-resolution width-modulated pulse rebalance electronics for strapdown gyroscopes and accelerometers

Three different rebalance electronic loops were designed, implemented, and evaluated. The loops were width-modulated binary types using a 614.4 kHz keying signal; they were developed to accommodate the following three inertial sensors with the indicated resolution values: (1) Kearfott 2412 accelerometer - resolution = 260 micro-g/data pulse, (2) Honeywell GG334 gyroscope - resolution = 3.9 milli-arc-sec/data pulse, (3) Kearfott 2401-009 accelerometer - resolution = 144 milli-g/data pulse. Design theory, details of the design implementation, and experimental results for each loop are presented

Power Management ICs for Internet of Things, Energy Harvesting and Biomedical Devices

This dissertation focuses on the power management unit (PMU) and integrated circuits (ICs) for the internet of things (IoT), energy harvesting and biomedical devices. Three monolithic power harvesting methods are studied for different challenges of smart nodes of IoT networks. Firstly, we propose that an impedance tuning approach is implemented with a capacitor value modulation to eliminate the quiescent power consumption. Secondly, we develop a hill-climbing MPPT mechanism that reuses and processes the information of the hysteresis controller in the time-domain and is free of power hungry analog circuits. Furthermore, the typical power-performance tradeoff of the hysteresis controller is solved by a self-triggered one-shot mechanism. Thus, the output regulation achieves high-performance and yet low-power operations as low as 12 µW. Thirdly, we introduce a reconfigurable charge pump to provide the hybrid conversion ratios (CRs) as 1⅓× up to 8× for minimizing the charge redistribution loss. The reconfigurable feature also dynamically tunes to maximum power point tracking (MPPT) with the frequency modulation, resulting in a two-dimensional MPPT. Therefore, the voltage conversion efficiency (VCE) and the power conversion efficiency (PCE) are enhanced and flattened across a wide harvesting range as 0.45 to 3 V. In a conclusion, we successfully develop an energy harvesting method for the IoT smart nodes with lower cost, smaller size, higher conversion efficiency, and better applicability. For the biomedical devices, this dissertation presents a novel cost-effective automatic resonance tracking method with maximum power transfer (MPT) for piezoelectric transducers (PT). The proposed tracking method is based on a band-pass filter (BPF) oscillator, exploiting the PT’s intrinsic resonance point through a sensing bridge. It guarantees automatic resonance tracking and maximum electrical power converted into mechanical motion regardless of process variations and environmental interferences. Thus, the proposed BPF oscillator-based scheme was designed for an ultrasonic vessel sealing and dissecting (UVSD) system. The sealing and dissecting functions were verified experimentally in chicken tissue and glycerin. Furthermore, a combined sensing scheme circuit allows multiple surgical tissue debulking, vessel sealer and dissector (VSD) technologies to operate from the same sensing scheme board. Its advantage is that a single driver controller could be used for both systems simplifying the complexity and design cost. In a conclusion, we successfully develop an ultrasonic scalpel to replace the other electrosurgical counterparts and the conventional scalpels with lower cost and better functionality

High Performance Power Management Integrated Circuits for Portable Devices

abstract: Portable devices often require multiple power management IC (PMIC) to power different sub-modules, Li-ion batteries are well suited for portable devices because of its small size, high energy density and long life cycle. Since Li-ion battery is the major power source for portable device, fast and high-efficiency battery charging solution has become a major requirement in portable device application. In the first part of dissertation, a high performance Li-ion switching battery charger is proposed. Cascaded two loop (CTL) control architecture is used for seamless CC-CV transition, time based technique is utilized to minimize controller area and power consumption. Time domain controller is implemented by using voltage controlled oscillator (VCO) and voltage controlled delay line (VCDL). Several efficiency improvement techniques such as segmented power-FET, quasi-zero voltage switching (QZVS) and switching frequency reduction are proposed. The proposed switching battery charger is able to provide maximum 2 A charging current and has an peak efficiency of 93.3%. By configure the charger as boost converter, the charger is able to provide maximum 1.5 A charging current while achieving 96.3% peak efficiency. The second part of dissertation presents a digital low dropout regulator (DLDO) for system on a chip (SoC) in portable devices application. The proposed DLDO achieve fast transient settling time, lower undershoot/overshoot and higher PSR performance compared to state of the art. By having a good PSR performance, the proposed DLDO is able to power mixed signal load. To achieve a fast load transient response, a load transient detector (LTD) enables boost mode operation of the digital PI controller. The boost mode operation achieves sub microsecond settling time, and reduces the settling time by 50% to 250 ns, undershoot/overshoot by 35% to 250 mV and 17% to 125 mV without compromising the system stability.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Integrated circuits for efficient power delivery using pulse-width-modulation

Circuits and architectures for efficient power delivery have become crucial in emerging smart systems. Switching power amplifiers (PA) are very attractive for such applications, because they exhibit better efficiency compared to linear PA designs, due to saturated operation. Switching PAs also allow for utilization of deep submicron CMOS technologies, due to which these designs can be easily integrated with digital circuits, and can benefit from process scaling, in performance as well as in area. Pulse-width-modulation (PWM) is commonly used with switching PAs. A PWM signal typically employs a high-frequency switching pulse waveform as a carrier signal, wherein the pulse-width or duty-cycle of each pulse is modulated by a given low-frequency input signal. The carrier frequency can vary from several kHz to GHz, and is typically determined by the target application. In this thesis, efficient power-delivery circuits that use PWM with switching class-D stages are presented. Advanced circuit techniques, as well as architectures for PWM are proposed to enhance efficiency and circumvent the limitations of conventional architectures. A digitally-intensive transmitter using RF-PWM with a class-D PA is described in the first part of the thesis. The use of carrier switching for alleviating the dynamic range limitation that can be observed in classical RF-PWM implementations is introduced. The approach employs the full carrier frequency for half of the amplitude range, and the second harmonic of half of the carrier frequency, for the remainder of the amplitude range. This concept not only allows the transmitter to drive modulated signals with large peak-to-average power ratio (PAPR), but also improves the back-off efficiency due to reduced switching losses in the half carrier-frequency mode. A glitch-free phase selector is proposed that removes the deleterious glitches that can occur at the input data transitions. The phase-selector also prevents D flip-flop setup-and-hold time violations. The transmitter has been implemented in a 130-nm CMOS process. The measured peak output power and power-added-efficiency (PAE) are 25.6 dBm and 34%, respectively. While driving 802.11g 20-MHz 64-QAM OFDM signals, the average measured output power is 18.3 dBm and the PAE is 16%, with an EVM of -25.5 dB. The second part of the thesis describes a high-speed driver that provides a PWM output using a class-D PA. A PLL-based architecture is employed which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used for PWM generation. Multi-level signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high PAPR. A differential, folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with additional supply source and sink paths, compared to 2-level operation. The PWM driver has been implemented in a 130-nm CMOS process and can operate with a switching frequency of 40-to-170 MHz. For 2/3/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is -61/-62/-53 dB and corresponding efficiency is 71/83/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2/3-level PA operation with a high PAPR signal with 500 kHz bandwidth. While intended as a general purpose amplifier, the approach is well-suited for applications such as power-line communications (PLC). The final part of the thesis introduces an efficient buck/buck-boost reconfigurable LED driver that supports PWM and PFM operation. The driver is based on peak current control. Rectified sin as well as sin² functions are employed in the reference signal to improve the power factor (PF) and total harmonic distortion (THD) of the buck and buck-boost converters. The design ensures that the peak of the inductor current maintains a constant level that is invariant for different AC line voltages. The operating mode of the design can be changed between PWM and PFM. The LED driver has been implemented in a 130-nm CMOS process. PF and THD are improved when the proposed reference is employed, and peak PF and lowest THD are 0.995/0.983/0.996 and 7.8/6.2/3.5% for the buck (PWM), buck (PFM), buck-boost (PFM) cases, respectively. The corresponding peak efficiency for the three cases is 88/92/91%, respectively.Electrical and Computer Engineerin

Design, Fabrication and Testing of Monolithic Low-Power Passive Sigma-Delta Analog-to-Digital Converters

Analog-to-digital converters are critically important in electronic systems. The difficulty in meeting high performance parameters increases as integrated circuit design process technologies advance into the deep nanometer region. Sigma-delta analog-todigital converters are an attractive option to fulfill many data converter requirements. These data converters offer high performance while relaxing requirements on the precision of components within an integrated circuit. Despite this, the active integrators found within sigma-delta analog-to-digital converters present two main challenges. These challenges are the power consumption of the active amplifier and achieving gain-bandwidth necessary for sigma-delta data converters in deep nanometer process technologies. Both of these challenges can be resolved through the replacement of active integrators with passive integrators at the expense of resolution. Three passive sigma-delta topologies were examined and characterized in detail. Two of these topologies were first-order and second-order noise shaping topologies. A new passive topology was developed which was determined to be optimal in resolution compared to the two traditional designs. This topology exhibits a first-order signal transfer function and a second-order noise transfer function. A method for increasing resolution of passive sigma-delta data converters despite inherent performance constraints was developed. Three example circuits were designed, fabricated and tested using On Semiconductor’s C5 500 nanometer CMOS process. These designs were optimized for low power and utilized memory sense amplifiers as quantizing elements. The first circuit, using passive lumped on-chip elements for the noise shaping network achieved a power consumption of 100 micro-watts and an effective resolution of 8-bits. The second circuit replaced the lumped components with switched-capacitor elements and achieved a power consumption of 6.75 micro-watts and an effective resolution of 9.3 bits. The third circuit was designed as a case study for the application of the proposed topology to “K-delta-1- sigma” modulators. This circuit achieved a power consumption of 10 milli-watts and an effective resolution of 8.5 bits