Experimental Evaluation and Comparison of Time-Multiplexed Multi-FPGA Routing Architectures

Emulating large complex designs require multi-FPGA systems (MFS). However, inter-FPGA communication is confronted by the challenge of lack of interconnect capacity due to limited number of FPGA input/output (I/O) pins. Serializing parallel signals onto a single trace effectively addresses the limited I/O pin obstacle. Besides the multiplexing scheme and multiplexing ratio (number of inter-FPGA signals per trace), the choice of the MFS routing architecture also affect the critical path latency. The routing architecture of an MFS is the interconnection pattern of FPGAs, fixed wires and/or programmable interconnect chips. Performance of existing MFS routing architectures is also limited by off-chip interface selection. In this dissertation we proposed novel 2D and 3D latency-optimized time-multiplexed MFS routing architectures. We used rigorous experimental approach and real sequential benchmark circuits to evaluate and compare the proposed and existing MFS routing architectures. This research provides a new insight into the encouraging effects of using off-chip optical interface and three dimensional MFS routing architectures. The vertical stacking results in shorter off-chip links improving the overall system frequency with the additional advantage of smaller footprint area. The proposed 3D architectures employed serialized interconnect between intra-plane and inter-plane FPGAs to address the pin limitation problem. Additionally, all off-chip links are replaced by optical fibers that exhibited latency improvement and resulted in faster MFS. Results indicated that exploiting third dimension provided latency and area improvements as compared to 2D MFS. We also proposed latency-optimized planar 2D MFS architectures in which electrical interconnections are replaced by optical interface in same spatial distribution. Performance evaluation and comparison showed that the proposed architectures have reduced critical path delay and system frequency improvement as compared to conventional MFS. We also experimentally evaluated and compared the system performance of three inter-FPGA communication schemes i.e. Logic Multiplexing, SERDES and MGT in conjunction with two routing architectures i.e. Completely Connected Graph (CCG) and TORUS. Experimental results showed that SERDES attained maximum frequency than the other two schemes. However, for very high multiplexing ratios, the performance of SERDES & MGT became comparable

Development of an ultra-fast X-ray camera using hybrid pixel detectors

L objectif du projet, dont le travail présenté dans cette thèse est une partie, était de développer une caméra à rayons X ultra-rapide utilisant des pixels hybrides pour l imagerie biomédicale et la science des matériaux. La technologie à pixels hybrides permet de répondre aux besoins des ces deux champs de recherche, en particulier en apportant la possibilité de sélectionner l énergie des rayons X détectés et de les imager à faible dose. Dans cette thèse, nous présentons une caméra ultra-rapide basée sur l utilisation de circuits intégrés XPAD3-S développés pour le comptage de rayons X. En collaboration avec l ESRF et SOLEIL, le CPPM a construit trois caméras XPAD3. Deux d entre elles sont utilisée sur les lignes de faisceau des synchrotrons SOLEIL et ESRF, et le troisième est installé dans le dispositif d irradiation PIXSCAN II du CPPM. La caméra XPAD3 est un détecteur de rayons X de grande surface composé de huit modules de détection comprenant chacun sept circuits XPAD3-S équipés d un système d acquisition de données ultra-rapide. Le système de lecture de la caméra est basé sur l interface PCI Express et sur l utilisation de circuits programmables FPGA. La caméra permet d obtenir jusqu à 240 images/s, le nombre maximum d images étant limité par la taille de la mémoire RAM du PC d acquisition. Les performances de ce dispositif ont été caractérisées grâce à plusieurs expériences à haut débit de lecture réalisées dans le système d irradiation PIXSCAN II. Celles-ci sont décrites dans le dernier chapitre de cette thèse.The aim of the project, of which the work described in this thesis is part, was to design a high-speed X-ray camera using hybrid pixels applied to biomedical imaging and for material science. As a matter of fact the hybrid pixel technology meets the requirements of these two research fields, particularly by providing energy selection and low dose imaging capabilities. In this thesis, high frame rate X-ray imaging based on the XPAD3-S photons counting chip is presented. Within a collaboration between CPPM, ESRF and SOLEIL, three XPAD3 cameras were built. Two of them are being operated at the beamline of the ESRF and SOLEIL synchrotron facilities and the third one is embedded in the PIXSCAN II irradiation setup of CPPM. The XPAD3 camera is a large surface X-ray detector composed of eight detection modules of seven XPAD3-S chips each with a high-speed data acquisition system. The readout architecture of the camera is based on the PCI Express interface and on programmable FPGA chips. The camera achieves a readout speed of 240 images/s, with maximum number of images limited by the RAM memory of the acquisition PC. The performance of the device was characterize by carrying out several high speed imaging experiments using the PIXSCAN II irradiation setup described in the last chapter of this thesis.AIX-MARSEILLE2-Bib.electronique (130559901) / SudocSudocFranceF

Reconfigurable network systems and software-defined networking

Modern high-speed networks have evolved from relatively static networks to highly adaptive networks facilitating dynamic reconfiguration. This evolution has influenced all levels of network design and management, introducing increased programmability and configuration flexibility. This influence has extended from the lowest level of physical hardware interfaces to the highest level of network management by software. A key representative of this evolution is the emergence of softwaredefined networking (SDN). In this paper, we review the current state of the art in reconfigurable network systems, covering hardware reconfiguration, SDN, and the interplay between them. We take a top-down approach, starting with a tutorial on software-defined networks. We then continue to discuss programming languages as the linking element between different levels of software and hardware in the network. We review electronic switching systems, highlighting programmability and reconfiguration aspects, and describe the trends in reconfigurable network elements. Finally, we describe the state of the art in the integration of photonic transceiver and switching elements with electronic technologies, and consider the implications for SDN and reconfigurable network systems.This work was jointly supported by the UKs Engineering and Physical Sciences Research Council (EPSRC) Internet Project EP/H040536/1, an EPSRC Research Fellowship grant to Philip Watts (EP/I004157/2), and DARPA and AFRL under contract FA8750-11-C-0249.This is the final version of the article. It first appeared from IEEE via http://dx.doi.org/10.1109/JPROC.2015.243573

Development, design and optimization of a novel Endcap DIRC for PANDA

PANDA, ein Experiment an der zukünftigen FAIR Anlage in Darmstadt, strebt die Spektroskopie von Hadronen mit hoher Präzision und Statistik an. Dazu wird die gluonenreiche Proton-Antiproton Annihilation im Bereich von 1.5 GeV/c bis 15 GeV/c genutzt. Eine möglichst vollständige Abdeckung des Raumwinkels mit allen Detektoren ist eine Grundvoraussetzung um dieses Ziel zu erreichen. Gegenstand dieser Dissertation ist das Systemdesign eines neuartigen DIRC Cherenkov Detektortyps zur Identifikation geladener Hadronen im Bereich der vorderen Endkappe des PANDA Target-Spektrometers. Ein besonderes Merkmal dieses Detektors ist die kompakte, planare Bauweise welche im Akzeptanzbereich (theta < 22°) weniger als 5 cm Platz in Strahlrichtung und ca. 20 cm am äußeren Rand benötigt, wo einzelphotonenabbildende Kameras platziert sind. Nach der Definition von Systemanforderungen wurde das System in logische Komponenten zerlegt. Für jede Komponente wurden mögliche Hardware- und Designoptionen identifiziert, analysiert und hinsichtlich ihrer Konformität mit den Systemanforderungen sowie ihrem Einfluss auf die Leistungsfähigkeit bewertet. Das optische System und Sensor-Layout wurden optimiert um einen Kompromiss zwischen Komplexität und Auflösung zu erlangen. Dieser Ansatz führte zu einem hochgradig modularen Detektordesign. Die resultierende Systemdefinition umfasst die Spezifikation des optischen Systems, der Sensoren und der Ausleseelektronik. Weiter wurde ein Konzept zur Implementierung eines Musterrekonstruktionsalgorithmus zur Online Analyse vorgeschlagen. Das neuartige Konzept erforderte die Entwicklung von speziellen Algorithmen zur Teilchenidentifikation, welche die effiziente Analyse der gemessenen zeitkorrelierten Photonenmuster ermöglichen. Diese Algorithmen wurden mit Signalen getestet, welche mit zeit-basierten Monte Carlo Simulationen generiert wurden um die Zeitcharakteristik der quasikontinuierlichen Interaktion bei der höchsten an PANDA erwarteten Rate nachzubilden. Die daraus folgende Schätzung der Detektoreffizienz ergibt eine Pi/K–Separation von bis zu 4sigma bei einem Impuls von 4 GeV/c.PANDA, an experiment at the upcoming FAIR facility in Germany, aims at hadron spectroscopy with high precision and rate by exploiting gluon-rich proton-antiproton collisions at momenta from 1.5 GeV/c to 15 GeV/c. Almost 4pi coverage by all detector components is a prerequisite to realize this goal. The objective of this thesis is the system design of a novel type of DIRC Cherenkov detector for particle identification at the forward endcap of the PANDA target spectrometer. A key feature of this detector is its compact, planar design which occupies less than 5 cm in beam direction at the acceptance region (theta < 22°) and about 20 cm at the outer rim where single-photon imaging cameras are located. After the definition of system requirements, the system has been dissected into individual logical components. For each component, possible hardware and design options have been identified, analyzed and evaluated for compliance with the requirements and their impact on the system performance. The optical system and sensor layout have been optimized to compromise complexity and performance, leading to a highly modular detector setup. The resulting definition of the design comprises the specification of the optical setup, the photosensor and the front-end electronics. Further, a concept for the implementation of the pattern reconstruction algorithm for online reconstruction has been proposed. The novel concept also required the development of dedicated particle identification algorithms which permit the efficient analysis of the measured time-correlated photon patterns. These algorithms have been tested with signals generated by means of time-based Monte Carlo simulations which resemble the time characteristics of the quasi-continuous interaction at the highest rate expected at PANDA. The resulting performance estimations predict a Pi/K–separation up to 4sigma at 4 GeV/c

The 30/20 GHz flight experiment system, phase 2. Volume 2: Experiment system description

A detailed technical description of the 30/20 GHz flight experiment system is presented. The overall communication system is described with performance analyses, communication operations, and experiment plans. Hardware descriptions of the payload are given with the tradeoff studies that led to the final design. The spacecraft bus which carries the payload is discussed and its interface with the launch vehicle system is described. Finally, the hardwares and the operations of the terrestrial segment are presented