RF techniques for IEEE 802.15.4: circuit design and device modelling

The RF circuitry in the physical layer of any wireless communication node is arguably its most important part. The front-end radio is the hardware that enables communication by transmitting and receiving information. Without a robust and high performance front-end, all other higher layers of signal processing and data handling in a wireless network are irrelevant. This thesis investigates the radio circuitry of wireless-networked nodes, and introduces several proposals for improvement. As an emerging market, analysis starts by examining available and ratified network standards suitable for low power applications. After identifying the IEEE 802.15.4 standard (commercially known as ZigBee) as the one of choice, and analysing several front-end architectures on which its transceiver circuitry can be based, an application, the Tyre Pressure Monitoring System (TPMS) is selected to examine the capabilities of the standard and its most suitable architecture in satisfying the application’s requirements. From this compatibility analysis, the most significant shortcomings are identified as interference and power consumption. The work presented in this thesis focuses on the power consumption issues. A comparison of available high frequency transistor technologies concludes Silicon CMOS to be the most appropriate solution for the implementation of low cost and low power ZigBee transceivers. Since the output power requirement of ZigBee is relatively modest, it is possible to consider the design of a single amplifier block which can act as both a Low Noise Amplifier (LNA) in the receiver chain and a Power Amplifier (PA) on the transmitter side. This work shows that by employing a suitable design methodology, a single dual-function amplifier can be realised which meets the required performance specification. In this way, power consumption and chip area can both be reduced, leading to cost savings so vital to the widespread utilisation of the ZigBee standard. Given the importance of device nonlinearity in such a design, a new transistor model based on independent representation of each of the transistor’s nonlinear elements is developed with the aim of quantifying the individual contribution of each of the transistors nonlinear elements, to the total distortion. The methodology to the design of the dual functionality (LNA/PA) amplifier starts by considering various low noise amplifier architectures and comparing them in terms of the trade-off between noise (required for LNA operation) and linearity (important for PA operation), and then examining the behaviour of the selected architecture (the common-source common-gate cascode) at higher than usual input powers. Due to the need to meet the far apart performance requirements of both the LNA and PA, a unique amplifier design methodology is developed The design methodology is based on simultaneous graphical visualisation of the relationship between all relevant performance parameters and corresponding design parameters. A design example is then presented to demonstrate the effectiveness of the methodology and the quality of trade-offs it allows the designer to make. The simulated performance of the final amplifier satisfies both the requirements of ZigBee’s low noise and power amplification. At 2.4GHz, the amplifier is predicted to have 1.6dB Noise Figure (NF), 6dBm Input-referred 3rd-order Intercept Point (IIP3), and 1dB compression point of -3.5dBm. In low power operation, it is predicted to have 10dB gain, consuming only 8mW. At the higher input power of 0dBm, it is predicted to achieve 24% Power-Added Efficiency (PAE) with 8dB gain and 22mW power consumption. Finally, this thesis presents a set of future research proposals based on problems identified throughout its development

Investigation of FACTS devices to improve power quality in distribution networks

Flexible AC transmission system (FACTS) technologies are power electronic solutions that improve power transmission through enhanced power transfer volume and stability, and resolve quality and reliability issues in distribution networks carrying sensitive equipment and non-linear loads. The use of FACTS in distribution systems is still in its infancy. Voltages and power ratings in distribution networks are at a level where realistic FACTS devices can be deployed. Efficient power converters and therefore loss minimisation are crucial prerequisites for deployment of FACTS devices. This thesis investigates high power semiconductor device losses in detail. Analytical closed form equations are developed for conduction loss in power devices as a function of device ratings and operating conditions. These formulae have been shown to predict losses very accurately, in line with manufacturer data. The developed formulae enable circuit designers to quickly estimate circuit losses and determine the sensitivity of those losses to device voltage and current ratings, and thus select the optimal semiconductor device for a specific application. It is shown that in the case of majority carrier devices (such as power MOSFETs), the conduction power loss (at rated current) increases linearly in relation to the varying rated current (at constant blocking voltage), but is a square root of the variable blocking voltage when rated current is fixed. For minority carrier devices (such as a pin diode or IGBT), a similar relationship is observed for varying current, however where the blocking voltage is altered, power losses are derived as a square root with an offset (from the origin). Finally, this thesis conducts a power loss-oriented evaluation of cascade type multilevel converters suited to reactive power compensation in 11kV and 33kV systems. The cascade cell converter is constructed from a series arrangement of cell modules. Two prospective structures of cascade type converters were compared as a case study: the traditional type which uses equal-sized cells in its chain, and a second with a ternary relationship between its dc-link voltages. Modelling (at 81 and 27 levels) was carried out under steady state conditions, with simplified models based on the switching function and using standard circuit simulators. A detailed survey of non punch through (NPT) and punch through (PT) IGBTs was completed for the purpose of designing the two cascaded converters. Results show that conduction losses are dominant in both types of converters in NPT and PT IGBTs for 11kV and 33kV systems. The equal-sized converter is only likely to be useful in one case (27-levels in the 33kV system). The ternary-sequence converter produces lower losses in all other cases, and this is especially noticeable for the 81-level converter operating in an 11kV network

Reliability Investigations of MOSFETs using RF Small Signal Characterization

Modern technology needs and advancements have introduced various new concepts such as Internet-of-Things, electric automotive, and Artificial intelligence. This implies an increased activity in the electronics domain of analog and high frequency. Silicon devices have emerged as a cost-effective solution for such diverse applications. As these silicon devices are pushed towards higher performance, there is a continuous need to improve fabrication, power efficiency, variability, and reliability. Often, a direct trade-off of higher performance is observed in the reliability of semiconductor devices. The acceleration-based methodologies used for reliability assessment are the adequate time-saving solution for the lifetime's extrapolation but come with uncertainty in accuracy. Thus, the efforts to improve the accuracy of reliability characterization methodologies run in parallel. This study highlights two goals that can be achieved by incorporating high-frequency characterization into the reliability characteristics. The first one is assessing high-frequency performance throughout the device's lifetime to facilitate an accurate description of device/circuit functionality for high-frequency applications. Secondly, to explore the potential of high-frequency characterization as the means of scanning reliability effects within devices. S-parameters served as the high-frequency device's response and mapped onto a small-signal model to analyze different components of a fully depleted silicon-on-insulator MOSFET. The studied devices are subjected to two important DC stress patterns, i.e., Bias temperature instability stress and hot carrier stress. The hot carrier stress, which inherently suffers from the self-heating effect, resulted in the transistor's geometry-dependent magnitudes of hot carrier degradation. It is shown that the incorporation of the thermal resistance model is mandatory for the investigation of hot carrier degradation. The property of direct translation of small-signal parameter degradation to DC parameter degradation is used to develop a new S-parameter based bias temperature instability characterization methodology. The changes in gate-related small-signal capacitances after hot carrier stress reveals a distinct signature due to local change of flat-band voltage. The measured effects of gate-related small-signal capacitances post-stress are validated through transient physics-based simulations in Sentaurus TCAD.:Abstract Symbols Acronyms 1 Introduction 2 Fundamentals 2.1 MOSFETs Scaling Trends and Challenges 2.1.1 Silicon on Insulator Technology 2.1.2 FDSOI Technology 2.2 Reliability of Semiconductor Devices 2.3 RF Reliability 2.4 MOSFET Degradation Mechanisms 2.4.1 Hot Carrier Degradation 2.4.2 Bias Temperature Instability 2.5 Self-heating 3 RF Characterization of fully-depleted Silicon on Insulator devices 3.1 Scattering Parameters 3.2 S-parameters Measurement Flow 3.2.1 Calibration 3.2.2 De-embedding 3.3 Small-Signal Model 3.3.1 Model Parameters Extraction 3.3.2 Transistor Figures of Merit 3.4 Characterization Results 4 Self-heating assessment in Multi-finger Devices 4.1 Self-heating Characterization Methodology 4.1.1 Output Conductance Frequency dependence 4.1.2 Temperature dependence of Drain Current 4.2 Thermal Resistance Behavior 4.2.1 Thermal Resistance Scaling with number of fingers 4.2.2 Thermal Resistance Scaling with finger spacing 4.2.3 Thermal Resistance Scaling with GateWidth 4.2.4 Thermal Resistance Scaling with Gate length 4.3 Thermal Resistance Model 4.4 Design for Thermal Resistance Optimization 5 Bias Temperature Instability Investigation 5.1 Impact of Bias Temperature Instability stress on Device Metrics 5.1.1 Experimental Details 5.1.2 DC Parameters Drift 5.1.3 RF Small-Signal Parameters Drift 5.2 S-parameter based on-the-fly Bias Temperature Instability Characterization Method 5.2.1 Measurement Methodology 5.2.2 Results and Discussion 6 Investigation of Hot-carrier Degradation 6.1 Impact of Hot-carrier stress on Device performance 6.1.1 DC Metrics Degradation 6.1.2 Impact on small-signal Parameters 6.2 Implications of Self-heating on Hot-carrier Degradation in n-MOSFETs 6.2.1 Inclusion of Thermal resistance in Hot-carrier Degradation modeling 6.2.2 Convolution of Bias Temperature Instability component in Hot-carrier Degradation 6.2.3 Effect of Source and Drain Placement in Multi-finger Layout 6.3 Vth turn-around effect in p-MOSFET 7 Deconvolution of Hot-carrier Degradation and Bias Temperature Instability using Scattering parameters 7.1 Small-Signal Parameter Signatures for Hot-carrier Degradation and Bias Temperature Instability 7.2 TCAD Dynamic Simulation of Defects 7.2.1 Fixed Charges 7.2.2 Interface Traps near Gate 7.2.3 Interface Traps near Spacer Region 7.2.4 Combination of Traps 7.2.5 Drain Series Resistance effect 7.2.6 DVth Correction 7.3 Empirical Modeling based deconvolution of Hot-carrier Degradation 8 Conclusion and Recommendations 8.1 General Conclusions 8.2 Recommendations for Future Work A Directly measured S-parameters and extracted Y-parameters B Device Dimensions for Thermal Resistance Modeling C Frequency response of hot-carrier degradation (HCD) D Localization Effect of Interface Traps Bibliograph

Compact modeling of gate tunneling leakage current in advanced nanoscale soi mosfets

En esta tesis se han desarrollado modelos compactos de corriente de fuga por túnel de puerta en SOI MOSFET (de simple y doble puerta) avanzados basados en una aproximación WKB de la probabilidad de túnel. Se han estudiado los materiales dieléctricos high-k más prometedores para los diferentes requisitos de nodos tecnológicos de acuerdo ala hoja de ruta ITRS de miniaturización de dispositivos electrónicos. Hemos presentado un modelo compacto de particionamiento de la corriente de fuga de puerta para un MOSFET nanométrico de doble puerta (DG MOSFET), utilizando modelos analíticos de la corriente de fuga por el túnel directo de puerta. Se desarrollaron también Los modelos analíticos dependientes de la temperatura de la corriente de túnel en la región de inversión y de la corriente túnel asistido por trampas en régimen subumbral. Finalmente, se desarrolló una técnica de extracción automática de parámetros de nuestro modelo compacto en DG MOSFET incluyendo efectos de canal corto. La corriente de la puerta por túnel directo y asistido por trampas modelada mediante los parámetros extraídos se verificó exitosamente mediante comparación con medidas experimentales

Power electronic interfaces for piezoelectric energy harvesters

Motion-driven energy harvesters can replace batteries in low power wireless sensors, however selection of the optimal type of transducer for a given situation is difficult as the performance of the complete system must be taken into account in the optimisation. In this thesis, a complete piezoelectric energy harvester system model including a piezoelectric transducer, a power conditioning circuit, and a battery, is presented allowing for the first time a complete optimisation of such a system to be performed. Combined with previous work on modelling an electrostatic energy harvesting system, a comparison of the two transduction methods was performed. The results at 100 Hz indicate that for small MEMS devices at low accelerations, electrostatic harvesting systems outperform piezoelectric but the opposite is true as the size and acceleration increases. Thus the transducer type which achieves the best power density in an energy harvesting system for a given size, acceleration and operating frequency can be chosen. For resonant vibrational energy harvesting, piezoelectric transducers have received a lot of attention due to their MEMS manufacturing compatibility with research focused on the transduction method but less attention has been paid to the output power electronics. Detailed design considerations for a piezoelectric harvester interface circuit, known as single-supply pre-biasing (SSPB), are developed which experimentally demonstrate the circuit outperforming the next best known interface's theoretical limit. A new mode of operation for the SSPB circuit is developed which improves the power generation performance when the piezoelectric material properties have degraded. A solution for tracking the maximum power point as the excitation changes is also presented.Open Acces

Characteristics features, economical aspects and environmental impacts of gen-4 nuclear power for developing countries

The growing demand of energy has delicate the requirement of alternative sources of energies other than fossil fuels. Though renewable energy resources like solar, biomass, hydro and geothermal energy appear as environment friendly, replenishing sources of energy, a comprehensive solution appears far-fetched as far as large scale production and wide-spread dissemination is concerned when long term cost factors are taken into consideration. In this paper, discussions on the advanced fourth generation nuclear power on the basis of environmental contamination, energy security, cost of fossil fuels and electricity generation and have philosophy to the prospects of nuclear power as the ultimate future energy option for the developing countries are done. This study proposes that gen-4 nuclear appears to be a long term environment favorable panacea to the much discoursed problem of energy crisis by maintaining energy security and long term cost concern in developing countries as well as in the whole world. Keywords: Gen-4 nuclear, reactor, kinetics, neutron, delayed neutron, transient

Modelling and Design of Inverter Threshold Quantization based Current Comparator using Artificial Neural Networks

Performance of a MOS based circuit is highly influenced by the transistor dimensions chosen for that circuit. Thus, proper dimensioning of the transistors plays a key role in determining its overall performance.  While choosing the dimension is critical, it is equally difficult, primarily due to complex mathematical formulations that come into play when moving into the submicron level. The drain current is the most affected parameter which in turn affects all other parameters. Thus, there is a constant quest to come up with techniques and procedure to simplify the dimensioning process while still keeping the parameters under check. This study presents one such novel technique to estimate the transistor dimensions for a current comparator structure, using the artificial neural networks approach. The approach uses Multilayer perceptrons as the artificial neural network architectures. The technique involves a two step process. In the first step, training and test data are obtained by doing SPICE simulations of modelled circuit using 0.18μm TSMC CMOS technology parameters. In the second step, this training and test data is applied to the developed neural network architecture using MATLAB R2007b

An Adaptable Interleaved DC-DC Boost Converter

A.H. Weinberg presented his classic boost topology in his 1974 publication intended for use in satellites. It comprises minimal external components and uses multiple coupled coil systems to provide a boost of up to 2x. Its simplicity makes it inherently robust and reliable as minimal components means lower chance of failure. While its simplicity makes it attractive it has limited boost capability which makes it unsuitable for many modern day applications. No significant investigation has been carried out on adapting the Weinberg topology for high boost operation so far as can be ascertained. An investigation into adapting the Weinberg converter for high boost operation is presented in this thesis. A novel topology is developed which preserves the simplicity, reliability and efficiency of the Weinberg design while achieving boost ratios >2x. An analysis of the proposed topology is provided and mathematical expressions are derived to quantify the voltages and currents in relevant component for a given set of operating conditions. All coupled windings share a single core and are arranged so the magnetic flux does not reverse direction which further reduces loss in the magnetic core material. The coupled coils clamp the MOSFET drain voltage to an amount much lower than the output voltage which allows lower breakdown versions with lower intrinsic ON-resistance to be used leading to reduced conduction losses. Modelling of circuit losses and their sources allows optimal selection and positioning of components and finds wound component and MOSFET conduction losses contribute around 70% of the total circuit loss. Modelling and trialling of wound component geometries is carried out to optimise magnetic coupling and reduce leakage inductance. Working prototypes are developed and used to verify the mathematical claims through experimentation. Overall system efficiency of 94.1% is achieved at a boost ratio of 8.8x and an output power of 257W. Overall system losses are reduced from 11% to 6% by simply optimising the magnetic assembly. However optimisation of the magnetic assembly is more involved and may be less tolerant to variation which may hinder repeatability but the results are very positive despite crude, hand-wound magnetic coils and standard quality silicon components being used; which is a promising sign