KEY FRONT-END CIRCUITS IN MILLIMETER-WAVE SILICON-BASED WIRELESS TRANSMITTERS FOR PHASED-ARRAY APPLICATIONS

Millimeter-wave (mm-Wave) phased arrays have been widely used in numerous wireless systems to perform beam forming and spatial filtering that can enhance the equivalent isotropically radiated power (EIRP) for the transmitter (TX). Regarding the existing phased-array architectures, an mm-Wave transmitter includes several building blocks to perform the desired delivered power and phases for wireless communication. Power amplifier (PA) is the most important building block. It needs to offer several advantages, e.g., high efficiency, broadband operation and high linearity. With the recent escalation of interest in 5G wireless communication technologies, mm-Wave transceivers at the 5G frequency bands (e.g., 28 GHz, 37 GHz, 39 GHz, and 60 GHz) have become an important topic in both academia and industry. Thus, PA design is a critical obstacle due to the challenges associated with implementing wideband, highly efficient and highly linear PAs at mm-Wave frequencies. In this dissertation, we present several PA design innovations to address the aforementioned challenges. Additionally, phase shifter (PS) also plays a key role in a phased-array system, since it governs the beam forming quality and steering capabilities. A high-performance phase shifter should achieve a low insertion loss, a wide phase shifting range, dense phase shift angles, and good input/output matching.Ph.D

Four-element phased-array beamformers and a self-interference canceling full-duplex transciver in 130-nm SiGe for 5G applications at 26 GHz

This thesis is on the design of radio-frequency (RF) integrated front-end circuits for next generation 5G communication systems. The demand for higher data rates and lower latency in 5G networks can only be met using several new technologies including, but not limited to, mm-waves, massive-MIMO, and full-duplex. Use of mm-waves provides more bandwidth that is necessary for high data rates at the cost of increased attenuation in air. Massive-MIMO arrays are required to compensate for this increased path loss by providing beam steering and array gain. Furthermore, full duplex operation is desirable for improved spectrum efficiency and reduced latency. The difficulty of full duplex operation is the self-interference (SI) between transmit (TX) and receive (RX) paths. Conventional methods to suppress this interference utilize either bulky circulators, isolators, couplers or two separate antennas. These methods are not suitable for fully-integrated full-duplex massive-MIMO arrays. This thesis presents circuit and system level solutions to the issues summarized above, in the form of SiGe integrated circuits for 5G applications at 26 GHz. First, a full-duplex RF front-end architecture is proposed that is scalable to massive-MIMO arrays. It is based on blind, RF self-interference cancellation that is applicable to single/shared antenna front-ends. A high resolution RF vector modulator is developed, which is the key building block that empowers the full-duplex frontend architecture by achieving better than state-of-the-art 10-b monotonic phase control. This vector modulator is combined with linear-in-dB variable gain amplifiers and attenuators to realize a precision self-interference cancellation circuitry. Further, adaptive control of this SI canceler is made possible by including an on-chip low-power IQ downconverter. It correlates copies of transmitted and received signals and provides baseband/dc outputs that can be used to adaptively control the SI canceler. The solution comes at the cost of minimal additional circuitry, yet significantly eases linearity requirements of critical receiver blocks at RF/IF such as mixers and ADCs. Second, to complement the proposed full-duplex front-end architecture and to provide a more complete solution, high-performance beamformer ICs with 5-/6- b phase and 3-/4-b amplitude control capabilities are designed. Single-channel, separate transmitter and receiver beamformers are implemented targeting massive- MIMO mode of operation, and their four-channel versions are developed for phasedarray communication systems. Better than state-of-the-art noise performance is obtained in the RX beamformer channel, with a full-channel noise figure of 3.3 d

Architectures, Antennas and Circuits for Millimeter-wave Wireless Full-Duplex Applications

Demand for wireless network capacity keeps growing exponentially every year, as a result a 1000-fold increase in data traffic is projected over the next 10 years in the context of 5G wireless networks. Solutions for delivering the 1000-fold increase in capacity fall into three main categories: deploying smaller cells, allocating more spectrum and improving spectral efficiency of wireless systems. Smaller cells at RF frequencies (1-6GHz) are unlikely to deliver the demanded capacity increase. On the other hand, millimeter-wave spectrum (frequencies over 24GHz) offers wider, multi-GHz channel bandwidths, and therefore has gained significant research interest as one of the most promising solutions to address the data traffic demands of 5G. Another disruptive technology is full-duplex which breaks a century-old assumption in wireless communication, by simultaneous transmission and reception on the same frequency channel. In doing so, full-duplex offers many benefits for wireless networks, including an immediate spectral efficiency improvement in the physical layer. Although FD promises great benefits, self-interference from the transmitter to its own receiver poses a fundamental challenge. The self-interference can be more than a billion times stronger than the desired signal and must be suppressed below the receiver noise floor. In recent years, there has been some research efforts on fully-integrated full-duplex RF transceivers, but mm-wave fully-integrated full-duplex systems, are still in their infancy. This dissertation presents novel architectures, antenna and circuit techniques to merge two exciting technologies, mm-wave and full-duplex, which can potentially offer the dual benefits of wide bandwidths and improved spectral efficiency. To this end, two different antenna interfaces, namely a wideband reconfigurable T/R antenna pair with polarization-based antenna cancellation and an mm-wave fully-integrated magnetic-free non-reciprocal circulator, are presented. The polarization-based antenna cancellation is employed in conjunction with the RF and digital cancellation to design a 60GHz full-duplex 45nm SOI CMOS transceiver with nearly 80dB self-interference suppression. The concepts and prototypes presented in this dissertation have also profound implications for emerging applications such as vehicular radars, 5G small-cell base-stations and virtual reality

Novel e-band reflection-type phase shifter - theory, design, and fabrication

This dissertation reports on the development of the E-band reflection-type phase shifters (RTPS), for applications in phased array systems. A novel 3-bit phase shifter is proposed consisting of a broadside coupled quadrature coupler and two reflective loads. This design utilizes a differential configuration providing the following benefits: 1. the easy accessibility of the on-chip short-circuit; 2. the reduction of electromagnetic interference; 3. the potential for expanding the 180° designed phase shift range to 360°, with the use of a phase inverter. Based on the fundamentals of microwave and millimetre-wave (mm-wave) circuits, theories and design methodologies of RTPS designs are discussed. Two metal layers realizing the coupler body and two extra metal layers for bridging connections of the differential microstrip lines are utilized in this design. At the reflective loads, radio frequency (RF) microelectromechanical system (MEMS) switch-controlled short-circuited microstrip lines with variable length are employed to achieve reduced loss and a large tuneable range. The phase shifter is fabricated with complex customized fabrication processes on 100 μm thick fused silica substrates. The 3-bit (9 states) differential RTPS was successfully fabricated and measured. Typically, a probe-based set-up with a 4-port vector network analyser (VNA) has to be used to measure a 4-port device; in our case, a new calibration method using differential probes with a 2-port VNA was proposed and validated. With a further characterization, by removing the measurement pads, using the distributed open-short de-embedding techniques, excellent RF performance was achieved for a tuneable phase range of 195.6° at 78 GHz. The measured reflection coefficients are below -18 dB, with an insertion loss error of less than 0.7 dB and a phase error of less than 8.6°, over the range of 70-86 GHz. At 74 GHz, the measured insertion loss varies from 3.9 dB to 4.9 dB, regarding all 9 phase states

Design methods for 60GHz beamformers in CMOS

The 60GHz band is promising for applications such as high-speed short-range wireless personal-area network (WPAN), real-time video streaming at rates of several-Gbps, automotive radar, and mm-Wave imaging, since it provides a large amount of bandwidth that can freely (i.e. without a license) be used worldwide. However, transceivers at 60GHz pose several additional challenges over microwave transceivers. In addition to the circuit design challenges of implementing high performance 60GHz RF circuits in mainstream CMOS technology, the path loss at 60GHz is significantly higher than at microwave frequencies because of the smaller size of isotropic antennas. This can be overcome by using phased array technology. This thesis studies the new concepts and design techniques that can be used for 60GHz phased array systems. It starts with an overview of various applications at mm-wave frequencies, such as multi-Gbps radio at 60GHz, automotive radar and millimeter-wave imaging. System considerations of mm-wave receivers and transmitters are discussed, followed by the selection of a CMOS technology to implement millimeter-wave (60GHz) systems. The link budget of a 60GHz WPAN is analyzed, which leads to the introduction of phased array techniques to improve system performance. Different phased array architectures are studied and compared. The system requirements of phase shifters are discussed. Several types of conventional RF phase shifters are reviewed. A 60GHz 4-bit passive phase shifter is designed and implemented in a 65nm CMOS technology. Measurement results are presented and compared to published prior art. A 60GHz 4-bit active phase shifter is designed and integrated with low noise amplifier and combiner for a phased array receiver. This is implemented in a 65nm CMOS technology, and the measurement results are presented. The design of a 60GHz 4-bit active phase shifter and its integration with power amplifier is also presented for a phased array transmitter. This is implemented in a 65nm CMOS technology. The measurement results are also presented and compared to reported prior art. The integration of a 60GHz CMOS amplifier and an antenna in a printed circuit-board (PCB) package is investigated. Experimental results are presented and discussed

Integrated Circuit and Antenna Technology for Millimeter-wave Phased Array Radio Front-end

Ever growing demands for higher data rate and bandwidth are pushing extremely high data rate wireless applications to millimeter-wave band (30-300GHz), where sufficient bandwidth is available and high data rate wireless can be achieved without using complex modulation schemes. In addition to the communication applications, millimeter-wave band has enabled novel short range and long range radar sensors for automotive as well as high resolution imaging systems for medical and security. Small size, high gain antennas, unlicensed and worldwide availability of released bands for communication and a number of other applications are other advantages of the millimeter-wave band. The major obstacle for the wide deployment of commercial wireless and radar systems in this frequency range is the high cost and bulky nature of existing GaAs- and InP-based solutions. In recent years, with the rapid scaling and development of the silicon-based integrated circuit technologies such as CMOS and SiGe, low cost technologies have shown acceptable millimeter-wave performance, which can enable highly integrated millimeter-wave radio devices and reduce the cost significantly. Furthermore, at this range of frequencies, on-chip antenna becomes feasible and can be considered as an attractive solution that can further reduce the cost and complexity of the radio package. The propagation channel challenges for the realization of low cost and reliable silicon-based communication devices at millimeter-wave band are severe path loss as well as shadowing loss of human body. Silicon technology challenges are low-Q passive components, low breakdown voltage of active devices, and low efficiency of on-chip antennas. The main objective of this thesis is to investigate and to develop antenna and front-end for cost-effective silicon based millimeter-wave phased array radio architectures that can address above challenges for short range, high data rate wireless communication as well as radar applications. Although the proposed concepts and the results obtained in this research are general, as an important example, the application focus in this research is placed on the radio aspects of emerging 60 GHz communication system. For this particular but extremely important case, various aspects of the technology including standard, architecture, antenna options and indoor propagation channel at presence of a human body are studied. On-chip dielectric resonator antenna as a radiation efficiency improvement technique for an on-chip antenna on low resistivity silicon is presented, developed and proved by measurement. Radiation efficiency of about 50% was measured which is a significant improvement in the radiation efficiency of on-chip antennas. Also as a further step, integration of the proposed high efficiency antenna with an amplifier in transmit and receive configurations at 30 GHz is successfully demonstrated. For the implementation of a low cost millimeter-wave array antenna, miniaturized, and efficient antenna structures in a new integrated passive device technology using high resistivity silicon are designed and developed. Front-end circuit blocks such as variable gain LNA, continuous passive and active phase shifters are investigated, designed and developed for a 60GHz phased array radio in CMOS technology. Finally, two-element CMOS phased array front-ends based on passive and active phase shifting architectures are proposed, developed and compared

CMOS Front-End Circuits in 45-nm SOI Suitable for Modular Phased-Array 60-GHz Radios

Next Fifth-generation (5G) wireless technologies enabling ultra-wideband spectrum availability and increased system capacity can achieve multi-gigabit/s (Gbps) data rates suitable for ultra-high-speed internet access around the 60-GHz band (i.e., Wi-Gig Technology). This mm-wave band is unlicensed and experiences high propagation power losses. Therefore, it is suitable for short-range communications and requires antenna arrays to satisfy the link budget requirements. Half-duplex reconfigurable phased-array transceivers require wideband, low-cost, highly integrated front-end circuits such as bilateral RF switches, low-noise/power amplifiers, passive RF splitters/combiners, and phase shifters implemented in deep sub-micron CMOS. In this dissertation, analysis, design, and verification of essential CMOS front-end components are covered and fabricated in GlobalFoundries 45-nm RF-SOI CMOS technology. Firstly, a fully-differential, single-pole, single-throw (SPST) switch capable of high isolation in broadband CMOS transceivers is described. The SPST switch realizes better than 50-dB isolation (ISO) across DC to 43 GHz while maintaining an insertion loss (IL) below 3 dB. Measured RF input power for 1-dB compression (IP1dB) of the IL is +19.6 dBm, and the measured input third-order intercept point (IIP3) is +30.4 dBm (both assuming differential inputs at 20 GHz). The prototype has an active area of 0.0058 mm^2. Secondly, a single-pole double-throw (SPDT) switch is implemented using the SPST concept by using a balun to convert the shared differential path to a single-ended antenna port. The SPDT simulations predict less than 3.5-dB IL and greater than 40-dB ISO across 55 to 65 GHz frequency band. An IP1dB of +21 dBm is expected from large-signal simulations. The prototype has an active area of 0.117 mm^2. Thirdly, a fully-differential switched-LC topology adopted with slow-wave artificial transmission line concept, and phase inversion network is described for a 360-degree phase shift range with 11.25-degree phase resolution. The average IL of the complete phase shifter is 5.3 dB with less than 1-dB rms IL error. Furthermore, the IP1dB of the phase shifter is +16 dBm. The prototype has an active area of 0.245 mm^2. Lastly, a fully-differential, 2-stage, common-source (CS) low-noise amplifier (LNA) is developed with wideband matching from 57.8 GHz to 67 GHz, a maximum simulated forward power gain of 20.8 dB, and a minimum noise figure of 3.07 dB. The LNA consumes 21 mW and predicts an OP1dB of 4.8 dBm from the 1-V supply. The LNA consumes an active area of 0.028 mm^2

Design of 28 GHz Low-Power Phased-Array Receiver Frontend in CMOS

This work presents the design and implementation of a low power phased-array receiver frontend at 28 GHz in 65 nm CMOS. The frontend incorporates a low- power low-noise amplifier(LNA) and a passive reflection-type phase shifter (RTPS) capable of providing 360° phase shift with 5-bit phase resolution and low loss variation. Passive phase-shifters in the literature suffer from trade-offs between finite phase resolution, insertion loss and phase shift range, and hence do not provide 360° phase range with uniform, low loss across phase shift settings. The proposed systematic design and load optimization approach leads to the RTPS achieving state-of-art performance in terms of insertion loss with 360° phase shift range, loss variation across phase shift and rms phase error. The low-power LNA is based on a transformer-coupled neutralization architecture that increases gain in each LNA stage, allowing for lower power consumption. The phased-array frontend is designed for Ka-band applications and has been characterized in 65nm CMOS from 26 GHz -30 GHz. The measured RTPS achieves 360 degrees phase shift with -7.75+/-0.3 dB and rms phase error of 0.3 degrees at 28 GHz. The low power phased-array receiver frontend has overall gain of 9.5 dB, gain variation of +/-0.4 dB and measured noise figure of 4.9 dB at 28 GHz. The receiver frontend consumes 10 mW from a 0.9 V supply with phase shifter and LNA active area of 0.16 mm² and 0.32 mm² respectively in 65nm CMOS, demonstrating its suitability for integration into low-power phased array receivers for emerging high data rate 5G wireless communication applications at 28 GHz

Lignes couplées à ondes lentes intégrées sur silicium en bande millimétrique - Application aux coupleurs, filtres et baluns

This work focuses on high-performances CS-CPW (Coupled Slow-wave CoPlanar Waveguide) transmission lines in classical CMOS integrated technologies for the millimiter-wave frequency band. First, the theory as well as the electrical models of the CS-CPW are presented. Thanks to the models and electromagnetic simulations, directional couplers with different coupling levels (3 dB, 10 dB, 18 dB) were designed in BiCMOS 55 nm technology. They have a good directivity, always better than 15 dB. A first prototype of a coupler was measured at 150 GHz presenting good agreement with the simulations. Next, coupled-line base filters were developed at 80 GHz using the CS-CPWs. Simulation present competitive results with the state-of-art: 11% of fractional bandwidth and a unload quality factor of 25. Finally, three projects started based on the CS-CPWs. The projects are currently used in two theses and one internship: a RTPS at 47 GHz, an isolator at 75 GHz and a balun at 80 GHz.L’objectif de ce travail de thèse est le développement en technologie intégrée standard d’une structure de ligne de transmission optimisée en termes de pertes, d’encombrement, de facteur de qualité et surtout du choix du niveau de couplage aux fréquences millimétriques. Cette structure a été nommée CS-CPW (Coupled Slow-wave CoPlanar Waveguide). Dans un premier temps, la théorie ainsi que les modèles électriques des CS-CPW sont présentés. Grâce aux modèles et aux simulations électromagnétiques, des coupleurs directionnels avec plusieurs valeurs de couplage (3 dB, 10 dB, 18 dB) ont été conçus en technologie BiCMOS 55 nm. Ils présentent tous une très bonne directivité, elle est toujours supérieure à 15 dB. Un premier prototype de coupleur a été mesuré à 150 GHz. Dans un deuxième temps, des filtres à la base des lignes couplées ont été développés à 80 GHz en utilisant des lignes CS-CPW. Les résultats des simulations présentent des résultats concurrentiels avec l’état de l’art : 11% de bande passante relative et un facteur non-chargé autour de 25. Finalement, trois projets ont démarré à la base de ces lignes. Ces projets sont actuellement utilisés dans deux travaux de thèse et un stage : un RTPS à 47 GHz, un isolateur à 75 GHz et un balun à 80 GHz