A micropower log domain FGMOS filter

In this paper, a CMOS implementation of a low voltage micropower logarithmic biquad based on floating gate MOS transistors (FGMOS) is presented. The translinear principle applied to the floating gate MOS transistor leads to an easy implementation of the state-space equations without using the source terminal in the loop. The voltage supply can be reduced and also there is no need of separate wells. The technique is proven in this low/band pass filter working at 1 V with a maximum power consumption of 2 /spl mu/W. The filter parameters can be adjusted in more than two decades, being the upper frequency around 150 kHz

Power-efficient current-mode analog circuits for highly integrated ultra low power wireless transceivers

In this thesis, current-mode low-voltage and low-power techniques have been applied to implement novel analog circuits for zero-IF receiver backend design, focusing on amplification, filtering and detection stages. The structure of the thesis follows a bottom-up scheme: basic techniques at device level for low voltage low power operation are proposed in the first place, followed by novel circuit topologies at cell level, and finally the achievement of new designs at system level. At device level the main contribution of this work is the employment of Floating-Gate (FG) and Quasi-Floating-Gate (QFG) transistors in order to reduce the power consumption. New current-mode basic topologies are proposed at cell level: current mirrors and current conveyors. Different topologies for low-power or high performance operation are shown, being these circuits the base for the system level designs. At system level, novel current-mode amplification, filtering and detection stages using the former mentioned basic cells are proposed. The presented current-mode filter makes use of companding techniques to achieve high dynamic range and very low power consumption with for a very wide tuning range. The amplification stage avoids gain bandwidth product achieving a constant bandwidth for different gain configurations using a non-linear active feedback network, which also makes possible to tune the bandwidth. Finally, the proposed current zero-crossing detector represents a very power efficient mixed signal detector for phase modulations. All these designs contribute to the design of very low power compact Zero-IF wireless receivers. The proposed circuits have been fabricated using a 0.5μm double-poly n-well CMOS technology, and the corresponding measurement results are provided and analyzed to validate their operation. On top of that, theoretical analysis has been done to fully explore the potential of the resulting circuits and systems in the scenario of low-power low-voltage applications.Programa Oficial de Doctorado en Tecnologías de las Comunicaciones (RD 1393/2007)Komunikazioen Teknologietako Doktoretza Programa Ofiziala (ED 1393/2007

A 1.25V FGMOS Filter Using Translinear Circuits

This paper presents a new low voltage/low power filter design based on Floating-Gate MOS (FGMOS) transistors. FGMOS transistors are used as primitives to design linear and non-linear (/spl radic/x) circuits. This technique enables a voltage reduction in strong inversion mode, and gives a new vision of the translinear principle, suitable for low voltage applications. Experimental results for 0.8 /spl mu/m low-pass and band-pass filter prototypes are reported

A Low-Voltage Floating-Gate MOS Biquad

A second-order gm-C filter based on the Floating-Gate MOS (FGMOS) technique is presented. It uses a new fully differential transconductor and works at 2 V of voltage supply with a full differential input linear range and a THD below 1%. Programming and tuning are performed by means of a single voltage signal. The transconductor incorporates a novel Common-Mode Feedback Circuit (CMFB) based also on FGMOS transistors.España, CICYT TIC-97-064

A 60 pW g(m)C Continuous Wavelet Transform Circuit for Portable EEG Systems

Accepted versio

Adaptive Log Domain Filters Using Floating Gate Transistors

In this thesis, an adaptive first order lowpass log domain filter and an adaptive second order log domain filter are presented with integrated learning rules for model reference estimation. Both systems are implemented using multiple input floating gate transistors to realize on-line learning of system parameters. Adaptive dynamical system theory is used to derive robust control laws in a system identification task for the parameters of both a first order lowpass filter and a second order tunable filter. The log domain filters adapt to estimate the parameters of the reference filters accurately and efficiently as the parameters are changed. Simulation results for both the first order and the second order adaptive filters are presented which demonstrate that adaptation occurs within milliseconds. Experimental results and mismatch analysis are described for the first order lowpass filter which demonstrates the success of our adaptive system design using this model-based learning method

Analogue micropower FET techniques review

A detailed introduction to published analogue circuit design techniques using Si and Si/SiGe FET devices for very low-power applications is presented in this review. The topics discussed include sub-threshold operation in FET devices, micro-current mirrors and cascode techniques, voltage level-shifting and class-AB operation, the bulk-drive approach, the floating-gate method, micropower transconductance-capacitance and log-domain filters and strained-channel FET technologies

Low Power Adaptive Circuits: An Adaptive Log Domain Filter and A Low Power Temperature Insensitive Oscillator Applied in Smart Dust Radio

This dissertation focuses on exploring two low power adaptive circuits. One is an adaptive filter at audio frequency for system identification. The other is a temperature insensitive oscillator for low power radio frequency communication. The adaptive filter is presented with integrated learning rules for model reference estimation. The system is a first order low pass filter with two parameters: gain and cut-off frequency. It is implemented using multiple input floating gate transistors to realize online learning of system parameters. Adaptive dynamical system theory is used to derive robust control laws in a system identification task. Simulation results show that convergence is slower using simplified control laws but still occurs within milliseconds. Experimental results confirm that the estimated gain and cut-off frequency track the corresponding parameters of the reference filter. During operation, deterministic errors are introduced by mismatch within the analog circuit implementation. An analysis is presented which attributes the errors to current mirror mismatch. The harmonic distortion of the filter operating in different inversion is analyzed using EKV model numerically. The temperature insensitive oscillator is designed for a low power wireless network. The system is based on a current starved ring oscillator implemented using CMOS transistors instead of LC tank for less chip area and power consumption. The frequency variance with temperature is compensated by the temperature adaptive circuits. Experimental results show that the frequency stability from 5°C to 65°C has been improved 10 times with automatic compensation and at least 1 order less power is consumed than published competitors. This oscillator is applied in a 2.2GHz OOK transmitter and a 2.2GHz phase locked loop based FM receiver. With the increasing needs of compact antenna, possible high data rate and wide unused frequency range of short distance communication, a higher frequency phase locked loop used for BFSK receiver is explored using an LC oscillator for its capability at 20GHz. The success of frequency demodulation is demonstrated in the simulation results that the PLL can lock in 0.5μs with 35MHz lock-in range and 2MHz detection resolution. The model of a phase locked loop used for BFSK receiver is analyzed using Matlab

Diseño de un Modulador ΣΔ en tiempo continuo utilizando el transistor de compuerta flotante

El presente trabajo aborda el diseño y desarrollo de un modulador ΣΔ en tiempo continuo en modo diferencial para la conversión analógica a digital de señales de baja frecuencia. El modulador es diseñado con circuitos que consumen baja potencia y bajo voltaje, utilizando transistores de compuerta flotante (FGMOS); cuya característica principal es que su voltaje de umbral es controlado por N voltajes de entrada acoplados a la compuerta flotante a través de capacitores. El sistema se integra para su realización microelectrónica utilizando diferentes bloques, tales como, integradores Gm-C operando como filtros pasa-bajos, un comparador operando como cuantizador de un bit y, pares diferenciales como convertidores de digital-analógico. Esto, conlleva a contar con técnicas de sobre muestreo con una alta velocidad de procesamiento en tiempo real. Por lo tanto, el diseño y desarrollo toma en cuenta técnicas de procesos CMOS de 0.5 μm, para su realizació