Integrated Transversal Equalizers in High-Speed Fiber-Optic Systems

Intersymbol interference (ISI) caused by intermodal dispersion in multimode fibers is the major limiting factor in the achievable data rate or transmission distance in high-speed multimode fiber-optic links for local area networks applications. Compared with optical-domain and other electrical-domain dispersion compensation methods, equalization with transversal filters based on distributed circuit techniques presents a cost-effective and low-power solution. The design of integrated distributed transversal equalizers is described in detail with focus on delay lines and gain stages. This seven-tap distributed transversal equalizer prototype has been implemented in a commercial 0.18-µm SiGe BiCMOS process for 10-Gb/s multimode fiber-optic links. A seven-tap distributed transversal equalizer reduces the ISI of a 10-Gb/s signal after 800 m of 50-µm multimode fiber from 5 to 1.38 dB, and improves the bit-error rate from about 10^-5 to less than 10^-12

Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin

System Level Modeling and Circuit Design for Low Voltage CMOS Equalizer for Coaxial Cable for Video Application

A new method of modeling coaxial cable frequency response with genetic algorithm was introduced. A system-level multi-stages adaptive equalizer model with QFB block was generated and tested with multiple cable models, pathological PRBS-23 data with data rate 1.5 GHz was used. This thesis also provided analysis of influences on output by using different parameters in simulations. Two adaptive equalizer circuits with different pre-amplifiers were implemented in GPDK 45 nm CMOS technology. Related simulations about adaptive ability, single stage compensation ability, and cascade stages compensation ability were completed. A tradeoff between output eye height and peak-to-peak jitter was discussed based on different simulations. Future work will be digital control circuit implementation, entire circuit fabrication, and testing