709 research outputs found

    On time, time synchronization and noise in time measurement systems

    Get PDF
    Time plays an important role in our modern lives. Especially having accurate time, which in turn depends on having clocks being synchronized to each other. This thesis is split into three distinct parts. The first part deals with the mathematical description of noise that is required to model clocks and electronics accurately. In particular we will address the problem that the generally used tools from signal theory fail for noise signals which are neither of finite energy nor periodic in nature. For this we will introduce a new function space based on the Pp-seminorm that is an extension of the Lp-norm for functions of potentially infinite energy but limited power. Using this new semi-norm we will modify the Fourier transform to work on signals from this P p-space. And last but not least, we will introduce, based on the above, a new mathematical model of noise that captures all the properties associated with 1/f -noise. In the second part, we will look at how noise propagates in a few classes of electronics, especially how the non-linear behavior of electronics leads to an amplification of noise and how it could be miti-gated. Lastly, in the third part we will look at one approach of fault-tolerant clock synchronization. After explaining its working principle and showing an implementation in an FPGA we will focus on meta-stability, the problems it can cause and how to handle them on two different circuit levels.Zeit spielt eine wichtige Rolle in unserem Leben. Insbesondere die VerfĂŒgbarkeit einer genauen Zeit. Welches wiederum davon abhĂ€ngt, dass man Uhren hat die auf einander synchronisiert laufen. Diese Arbeit ist in drei Teile aufgeteilt: Im ersten Teil betrachten wir die mathematische Beschreibung von Rauschen um elektronische Systeme und Uhren korrekt beschreiben zu können. Im Besonderen betrachten wir die Probleme die die generell benutzten Methoden der Signalverarbeitung beim Umgang mit Rauschsignalen haben, die weder energiebegrenzt noch periodisch sind. DafĂŒr erweitern wir den Funktionenraum der Lp-Norm auf leistungslimiterte Funktionene und fĂŒhren die Pp-Halbnorm ein und modifizieren die Fouriertransformation zur Verwendung auf diesen Raum. Und letztlich fĂŒhren wir ein neues mathematisches Model zur Beschreibung von Rauschen ein, welches alle ĂŒblicherweise angenommenen Eigenschaften gleichzeitig erfĂŒllt. Im zweiten Teil analysieren wir wie sich einige Klassen von elektronischen Schaltungem im Bezug auf Rauschen verhalten. Insbesondere im Bezug auf das nicht-lineare Verhalten der elektronischen Elemente, welches zu einer VerstĂ€rkung des Rauschens fĂŒhrt. Im dritten Teil betrachten wir eine Möglichkeit um fehlertolerante Synchronization von Uhren zu erreichen. Nach einem Überblick ĂŒber den verwendeten Algorithmus und wie dieser einem FPGA implementiert werden kann, schauen wir uns den Einfluss von MetastabilitĂ€t an und wie dieser eingedĂ€mmt werden kann

    Development of a 6-bit 15.625 MHz CMOS two-step flash analog-to-digital converter for a low dead time sub-nanosecond time measurement system

    Get PDF
    The development of a 6-bit 15.625 MHz CMOS two-step analog-to-digital converter (ADC) is presented. The ADC was developed for use in a low dead time, high-performance, sub-nanosecond time-to-digital converter (TDC). The TDC is part of a new custom CMOS application specific integrated circuit (ASIC) that will be incorporated in the next generation of front-end electronics for high-performance positron emission tomography imaging. The ADC is based upon a two-step flash architecture that reduces the comparator count by a factor-of-two when compared to a traditional flash ADC architecture and thus a significant reduction in area, power dissipation, and input capacitance of the converter is achieved. The converter contains time-interleaved auto-zeroed CMOS comparators. These comparators utilize offset correction in both the preamplifier and the subsequent regenerative latch stage to guarantee good integral and differential non-linearity performance of the converter over extreme process conditions. Also, digital error correction was employed to overcome most of the major metastability problems inherent in flash converters and to guarantee a completely monotonic transfer function. Corrected comparator offset measurements reveal that the CMOS comparator design maintains a worse case input-referred offset of less than 1 mV at conversion rates up to 8 MHz and less than a 2 mV offset at conversion rates as high as 16 MHz while dissipating less than 2.6 mW. Extensive laboratory measurements indicate that the ADC achieves differential and integral non-linearity performance of less than ±1/2 LSB with a 20 mV/LSB resolution. The ADC dissipates 90 mW from a single 5 V supply and occupies a die area of 1.97 mm x 1.13 mm in 0.8 Όm CMOS technology

    Design of Energy-Efficient A/D Converters with Partial Embedded Equalization for High-Speed Wireline Receiver Applications

    Get PDF
    As the data rates of wireline communication links increases, channel impairments such as skin effect, dielectric loss, fiber dispersion, reflections and cross-talk become more pronounced. This warrants more interest in analog-to-digital converter (ADC)-based serial link receivers, as they allow for more complex and flexible back-end digital signal processing (DSP) relative to binary or mixed-signal receivers. Utilizing this back-end DSP allows for complex digital equalization and more bandwidth-efficient modulation schemes, while also displaying reduced process/voltage/temperature (PVT) sensitivity. Furthermore, these architectures offer straightforward design translation and can directly leverage the area and power scaling offered by new CMOS technology nodes. However, the power consumption of the ADC front-end and subsequent digital signal processing is a major issue. Embedding partial equalization inside the front-end ADC can potentially result in lowering the complexity of back-end DSP and/or decreasing the ADC resolution requirement, which results in a more energy-effcient receiver. This dissertation presents efficient implementations for multi-GS/s time-interleaved ADCs with partial embedded equalization. First prototype details a 6b 1.6GS/s ADC with a novel embedded redundant-cycle 1-tap DFE structure in 90nm CMOS. The other two prototypes explain more complex 6b 10GS/s ADCs with efficiently embedded feed-forward equalization (FFE) and decision feedback equalization (DFE) in 65nm CMOS. Leveraging a time-interleaved successive approximation ADC architecture, new structures for embedded DFE and FFE are proposed with low power/area overhead. Measurement results over FR4 channels verify the effectiveness of proposed embedded equalization schemes. The comparison of fabricated prototypes against state-of-the-art general-purpose ADCs at similar speed/resolution range shows comparable performances, while the proposed architectures include embedded equalization as well

    A 2 GHz Bandpass Analog to Digital Delta-sigma Modulator for CDMA Receivers with 79 DB Dynamic Range in 1.23 MHz Bandwidth

    Full text link
    This paper presents the design of a second-order single-bit analog-to-digital continuous-time delta-sigma modulator that can be used in wireless CDMA receivers. The continuous-time delta-sigma modulator samples at 2 GHz, consumes 18 mW at 1.8 V and has a 79-dB signal-to-noise ratio (SNR) over a 1.23-MHz bandwidth. The continuous-time delta-sigma modulator was fabricated in a 0.18- m 1-poly 6-metal, CMOS technology and has an active area of approximately 0.892 mm2 . The delta-sigma modulator\u27s critical performance speciïŹcations are derived from the CDMA receiver speciïŹcations

    DIGITALLY ASSISTED TECHNIQUES FOR NYQUIST RATE ANALOG-to-DIGITAL CONVERTERS

    Get PDF
    With the advance of technology and rapid growth of digital systems, low power high speed analog-to-digital converters with great accuracy are in demand. To achieve high effective number of bits Analog-to-Digital Converter(ADC) calibration as a time consuming process is a potential bottleneck for designs. This dissertation presentsa fully digital background calibration algorithm for a 7-bit redundant flash ADC using split structure and look-up table based correction. Redundant comparators are used in the flash ADC design of this work in order to tolerate large offset voltages while minimizing signal input capacitance. The split ADC structure helps by eliminating the unknown input signal from the calibration path. The flash ADC has been designed in 180nm IBM CMOS technology and fabricated through MOSIS. This work was supported by Analog Devices, Wilmington,MA. While much research on ADC design has concentrated on increasing resolution and sample rate, there are many applications (e.g. biomedical devices and sensor networks) that do not require high performance but do require low power energy efficient ADCs. This dissertation also explores on design of a low quiescent current 100kSps Successive Approximation (SAR) ADC that has been used as an error detection ADC for an automotive application in 350nm CD (CMOS-DMOS) technology. This work was supported by ON Semiconductor Corp, East Greenwich,RI

    Timing Measurement Platform for Arbitrary Black-Box Circuits Based on Transition Probability

    No full text

    Broadband Continuous-time MASH Sigma-Delta ADCs

    Get PDF
    • 

    corecore