Manual for Automation of Dc-microgrid Component Using Matlab/Simulink and FPGA\u27s

Solar Energy is one of the abundantly available renewable energy source. Solar panels are semiconductor materials which capture the solar energy from every band in the visible light spectrum, infrared spectrum and ultra violet spectrum and converts it into electrical energy. The DC community microgrid is used to supplement utility electrical power supplied to the neighbored with renewable sources such as solar panels, emergency back-up power through batteries or generators. Smart Cloud Interconnected environment increases the standard of living and facilitates ease to rectify faults, debug components and reinstate or replace obsolete components with newer ones. Automation of the DC microgrid components provides a simple yet efficient way to connect to the grid and to every component in the grid remotely. It is essential to find the node of failure in the grid for technicians and engineers to work on and to debug the issue to facilitate smooth running of the grid without shutdown. FPGAs are used as target devices for end synthesis of the model that is created on Simulink. These FPGAs are links between cloud and power electronics components. To utilize the energy resource efficiently we need to monitor the input and output of every component at every node in the grid. Simulating models on Simulink will let us connect the component and test engineer to the grid to detect any flaws or failures on time. FPGAs are easily reprogrammable and have long life with excellent capability to withstand stress. This thesis report provides a set of procedures to create and simulate a real time component model and to generate HDL files to build a clean code which can be redeployed on target FPGAs

The STAR MAPS-based PiXeL detector

The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014-2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this paper

Data Conversion Within Energy Constrained Environments

Within scientific research, engineering, and consumer electronics, there is a multitude of new discrete sensor-interfaced devices. Maintaining high accuracy in signal quantization while staying within the strict power-budget of these devices is a very challenging problem. Traditional paths to solving this problem include researching more energy-efficient digital topologies as well as digital scaling.;This work offers an alternative path to lower-energy expenditure in the quantization stage --- content-dependent sampling of a signal. Instead of sampling at a constant rate, this work explores techniques which allow sampling based upon features of the signal itself through the use of application-dependent analog processing. This work presents an asynchronous sampling paradigm, based off the use of floating-gate-enabled analog circuitry. The basis of this work is developed through the mathematical models necessary for asynchronous sampling, as well the SPICE-compatible models necessary for simulating floating-gate enabled analog circuitry. These base techniques and circuitry are then extended to systems and applications utilizing novel analog-to-digital converter topologies capable of leveraging the non-constant sampling rates for significant sample and power savings

Exploiting intra-warp address monotonicity for fast memory coalescing in GPUs

Graphics Processing Units (GPUs) are growing increasingly popular as general purpose compute accelerators. GPUs are best suited for applications which have abundant data parallelism wherein the computation expressed as a single thread can be applied over a large set of data items. One key constraint that affects application performance on GPUs is that the underlying hardware is single-instruction, multiple data (SIMD) hardware which requires parallel instructions from the multiple threads to execute in a lock-step manner. The benefits of lock-step execution can be seriously degraded if the threads diverge (because of memory or branches). Specifically in the case of memory, the addresses from each thread in a SIMD wavefront/warp must be coalesced to enable parallel memory access to minimize divergence. ^ The general problem of coalescing assumes arbitrary address distribution which can be slow. This thesis aims to exploit intra-warp address monotonicity (as measured in a recent study by Holic) to achieve fast memory coalescing. Holic\u27s study reveals the intra-warp addresses are monotonically increasing or decreasing in the common case. The key contributions of this thesis are twofold. First, I design novel hardware coalescing mechanisms to achieve fast-coalescing and quantify the area/delay of my coalescing designs. Second, I quantify the impact of fast-coalescing on overall GPU performance for a suite of GPU benchmarks

Design and Implementation of Panel Logic for Power Plant Simulators

This study involves the simulation and implementation of panel logic for Georgia Power Comany simulator, used for training operators. The implementation and coding in FORTRAN involves several steps of simplifying the functional control drawings (FCD 1 s) provided by the utility company, and reduced to a format, generally known as implemetnation drawings from which a program is written. The program is executed in real-time on the simulator. The authenticity of the panel logic must conform to the actual power plant logic strictly, and its response must be identical both under normal operation and under existing malfunction conditions. Boolean algebra is used extensively to simplify the logic operations and reduce the real-time code. When the program logic was merged with the rest of the simulator completely, its behavior and response to operator inputs from control panel and interaction with other process models was found to be exactly what would happen in the actual plant. This program logic could be run on an event-oriented basis instead of cyclic basis, and this could prove helpful in future simulations.Computing and Information Scienc

System integration and verification of GNSS baseband processor

Satellite navigation, in the last three decades, has seen an evolution bringing up entirely new systems (Galileo) and modernization of existing systems (Global Positioning System). These systems have now changed the environment of the receiver design resulting in the development of Global Navigation Satellite System (GNSS) with new signal processing algorithms. GNSS receiver receives the signals from a GNSS satellite constellation, digitally processes them and provides position, velocity and time. Hardware GNSS receivers have good efficiency, good computational load and low power consumption. Such a hardware GNSS receiver is presented here. GNSS Receiver Reference Design is a fully functional L1 only GNSS receiver design. The main objective for this design is to make fully open access architecture (HW + SW) available to industry partners and researchers for development of GNSS and GNSSenhanced devices, for investigating current GNSS receivers and receiver algorithms and upcoming GNSS receiver standards. Baseband processing generates pre-processed data from received signals. It comprises digital signal processing executed by custom hardware (baseband system) and control processing implemented by a soft-core processor (COFFEE RISC core). The baseband system component performs acquisition and tracking of 6 channels. It currently provides only GPS coarse/acquisition (C/A) code. It is implemented by Field Programmable Gate Array (FPGA) logic, supported by hardware macros. The baseband system and the processor are to be integrated efficiently to manage the receiver activity. The integration is achieved by designing an interface that is compatible with the standard bus architecture. The interface is a shared system bus that contains a register database. The interface is implemented in RTL and verified in functional simulations. In this thesis, another objective of verifying the baseband system is achieved by targeting the maximum code coverage. The results show that this improves the quality of verification and provides good confidence in the design. The coverage numbers prove that the verification is extensive, close to 100%. Finally, synthesis is also needed for verifying the design implementation on gate level. Since the baseband system included many of Xilinx based models, both the subsystems are synthesized on Xilinx Virtex-II Pro platform. The synthesis results provide information on the on-chip area consumption