Novel Current-Mode Sensor Interfacing and Radio Blocks for Cell Culture Monitoring

Since 2004 Imperial College has been developing the world’s first application-specific instrumentation aiming at the on-line, in-situ, physiochemical monitoring of adult stem cell cultures. That effort is internationally known as the ‘Intelligent Stem Cell Culture Systems’ (ISCCS) project. The ISCCS platform is formed by the functional integration of biosensors, interfacing electronics and bioreactors. Contrary to the PCB-level ISCCS platform the work presented in this thesis relates to the realization of a miniaturized cell culture monitoring platform. Specifically, this thesis details the synthesis and fabrication of pivotal VLSI circuit blocks suitable for the construction of a miniaturized microelectronic cell monitoring platform. The thesis is composed of two main parts. The first part details the design and operation of a two-stage current-input currentoutput topology suitable for three-electrode amperometric sensor measurements. The first stage is a CMOS-dual rail-class AB-current conveyor providing a low impedancevirtual ground node for a current input. The second stage is a novel hyperbolic-sinebased externally-linear internally-non-linear current amplification stage. This stage bases its operation upon the compressive sinh−1 conversion of the interfaced current to an intermediate auxiliary voltage and the subsequent sinh expansion of the same voltage. The proposed novel topology has been simulated for current-gain values ranging from 10 to 1000 using the parameters of the commercially available 0.8μm AMS CMOS process. Measured results from a chip fabricated in the same technology are also reported. The proposed interfacing/amplification architecture consumes 0.88-95μW. The second part describes the design and practical evaluation of a 13.56MHz frequency shift keying (FSK) short-range (5cm) telemetry link suitable for the monitoring of incubated cultures. Prior to the design of the full FSK radio system, a pair of 13.56MHz antennae are characterized experimentally. The experimental S-parameter-value determination of the 13.56MHz wireless link is incorporated into the Cadence Design Framework allowing a high fidelity simulation of the reported FSK radio. The transmitter of the proposed system is a novel multi-tapped seven-stage ring-oscillator-based VCO whereas the core of the receiver is an appropriately modified phase locked loop (PLL). Simulated and measured results from a 0.8μm CMOS technology chip are reported

A Low-Power Wireless Multichannel Microsystem for Reliable Neural Recording.

This thesis reports on the development of a reliable, single-chip, multichannel wireless biotelemetry microsystem intended for extracellular neural recording from awake, mobile, and small animal models. The inherently conflicting requirements of low power and reliability are addressed in the proposed microsystem at architectural and circuit levels. Through employing the preliminary microsystems in various in-vivo experiments, the system requirements for reliable neural recording are identified and addressed at architectural level through the analytical tool: signal path co-optimization. The 2.85mm×3.84mm, mixed-signal ASIC integrates a low-noise front-end, programmable digital controller, an RF modulator, and an RF power amplifier (PA) at the ISM band of 433MHz on a single-chip; and is fabricated using a 0.5µm double-poly triple-metal n-well standard CMOS process. The proposed microsystem, incorporating the ASIC, is a 9-channel (8-neural, 1-audio) user programmable reliable wireless neural telemetry microsystem with a weight of 2.2g (including two 1.5V batteries) and size of 2.2×1.1×0.5cm3. The electrical characteristics of this microsystem are extensively characterized via benchtop tests. The transmitter consumes 5mW and has a measured total input referred voltage noise of 4.74µVrms, 6.47µVrms, and 8.27µVrms at transmission distances of 3m, 10m, and 20m, respectively. The measured inter-channel crosstalk is less than 3.5% and battery life is about an hour. To compare the wireless neural telemetry systems, a figure of merit (FoM) is defined as the reciprocal of the power spent on broadcasting one channel over one meter distance. The proposed microsystem’s FoM is an order of magnitude larger compared to all other research and commercial systems. The proposed biotelemetry system has been successfully used in two in-vivo neural recording experiments: i) from a freely roaming South-American cockroach, and ii) from an awake and mobile rat.Ph.D.Electrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttp://deepblue.lib.umich.edu/bitstream/2027.42/91542/1/aborna_1.pd

A Low-Power BFSK/OOK Transmitter for Wireless Sensors

In recent years, significant improvements in semiconductor technology have allowed consistent development of wireless chipsets in terms of functionality and form factor. This has opened up a broad range of applications for implantable wireless sensors and telemetry devices in multiple categories, such as military, industrial, and medical uses. The nature of these applications often requires the wireless sensors to be low-weight and energy-efficient to achieve long battery life. Among the various functions of these sensors, the communication block, used to transmit the gathered data, is typically the most power-hungry block. In typical wireless sensor networks, transmission range is below 10 meters and required radiated power is below 1 milliwatt. In such cases, power consumption of the frequency-synthesis circuits prior to the power amplifier of the transmitter becomes significant. Reducing this power consumption is currently the focus of various research endeavors. A popular method of achieving this goal is using a direct-modulation transmitter where the generated carrier is directly modulated with baseband data using simple modulation schemes. Among the different variations of direct-modulation transmitters, transmitters using unlocked digitally-controlled oscillators and transmitters with injection or resonator-locked oscillators are widely investigated because of their simple structure. These transmitters can achieve low-power and stable operation either with the help of recalibration or by sacrificing tuning capability. In contrast, phase-locked-loop-based (PLL) transmitters are less researched. The PLL uses a feedback loop to lock the carrier to a reference frequency with a programmable ratio and thus achieves good frequency stability and convenient tunability. This work focuses on PLL-based transmitters. The initial goal of this work is to reduce the power consumption of the oscillator and frequency divider, the two most power-consuming blocks in a PLL. Novel topologies for these two blocks are proposed which achieve ultra-low-power operation. Along with measured performance, mathematical analysis to derive rule-of-thumb design approaches are presented. Finally, the full transmitter is implemented using these blocks in a 130 nanometer CMOS process and is successfully tested for low-power operation

Cmos Rotary Traveling Wave Oscillators (Rtwos)

Rotary Traveling Wave Oscillator (RTWO) represents a transmission line based technology for multi-gigahertz multiple phase clock generation. RTWO is known for providing low jitter and low phase noise signals but the issue of high power consumption is a major drawback in its application. Direction of wave propagation is random and is determined by the least resistance path in the absence of an external direction control circuit. The objective of this research is to address some of the problems of RTWO design, including high power consumption, uncertainty of propagation direction and optimization of design variables. Included is the modeling of RTWO for sensitivity, phase noise and power analysis. Research objectives were met through design, simulation and implementation. Different designs of RTWO in terms of ring size and number of amplifier stages were implemented and tested. Design tools employed include Agilent ADS, Cadence EDA, SONNET and Altium PCB Designer. Test chip was fabricated using IBM 0.18 μm RF CMOS technology. Performance measures of interest are tuning range, phase noise and power consumption. Agilent ADS and SONNET were used for electromagnetic modeling of transmission lines and electromagnetic field radiation. For each design, electromagnetic simulations were carried out followed by oscillation synthesis based on circuit simulation in Cadence Spectre. RTWO frequencies between 2 GHz and 12 GHz were measured based on the ring size of transmission lines. Simulated microstrip transmission line segments had a quality factor between 5.5 and 18. For the various designs, power consumption ranged from 20 mW to 120 mW. Measured phase noise ranged between -123 dBc/Hz and -87 dBc/Hz at 1 MHz offset. Development also included the design of a wide band buffer and a printed circuit board with high signal integrity for accurate measurement of oscillation frequency and other performance measures. Simulated performance, schematics and measurement results are presented

Periodically Disturbed Oscillators

By controlling the timing of events and enabling the transmission of data over long distances, oscillators can be considered to generate the "heartbeat" of modern electronic systems. Their utility, however, is boosted significantly by their peculiar ability to synchronize to external signals that are themselves periodic in time. Although this fascinating phenomenon has been studied by scientists since the 1600s, models for describing this behavior have seen a disconnect between the rigorous, methodical approaches taken by mathematicians and the design-oriented, physically-based analyses carried out by engineers. While the analytical power of the former is often concealed by an inundation of abstract mathematical machinery, the accuracy and generality of the latter are constrained by the empirical nature of the ensuing derivations. We hope to bridge that gap here. In this thesis, a general theory of electrical oscillators under the influence of a periodic injection is developed from first principles. Our approach leads to a fundamental yet intuitive understanding of the process by which oscillators lock to a periodic injection, as well as what happens when synchronization fails and the oscillator is instead injection pulled. By considering the autonomous and periodically time-varying nature that underlies all oscillators, we build a time-synchronous model that is valid for oscillators of any topology and periodic disturbances of any shape. A single first-order differential equation is shown to be capable of making accurate, quantitative predictions about a wide array of properties of periodically disturbed oscillators: the range of injection frequencies for which synchronization occurs, the phase difference between the injection and the oscillator under lock, stable vs. unstable modes of locking, the pull-in process toward lock, the dynamics of injection pulling, as well as phase noise in both free-running and injection-locked oscillators. The framework also naturally accommodates superharmonic injection-locked frequency division, subharmonic injection-locked frequency multiplication, and the general case of an arbitrary rational relationship between the injection and oscillation frequencies. A number of novel insights for improving the performance of systems that utilize injection locking are also elucidated. In particular, we explore how both the injection waveform and the oscillator's design can be modified to optimize the lock range. The resultant design techniques are employed in the implementation of a dual-moduli prescaler for frequency synthesis applications which features low power consumption, a wide operating range, and a small chip area. For the commonly used inductor-capacitor (LC) oscillator, we make a simple modification to our framework that takes the oscillation amplitude into account, greatly enhancing the model's accuracy for large injections. The augmented theory uniquely captures the asymmetry of the lock range as well as the distinct characteristics exhibited by different types of LC oscillators. Existing injection locking and pulling theories in the available literature are subsumed as special cases of our model. It is important to note that even though the veracity of our theoretical predictions degrades as the size of the injection grows due to our framework's linearization with respect to the disturbance, our model's validity across a broad range of practical injection strengths are borne out by simulations and measurements on a diverse collection of integrated LC, ring, and relaxation oscillators. Lastly, we also present a phasor-based analysis of LC and ring oscillators which yields a novel perspective into how the injection current interacts with the oscillator's core nonlinearity to facilitate injection locking.</p

SILICON TERAHERTZ ELECTRONICS: CIRCUITS AND SYSTEMS FOR FUTURE APPLICATIONS

The terahertz frequency bands are gaining increasing attention these days for the potential applications in imaging, sensing, spectroscopy, and communication. These applications can be used in a wide range of fields, such as military, security, biomedical analysis, material science, astronomy, etc. Unfortunately, utilizing these frequency bands is very challenging due to the notorious ”terahertz gap”. Consequently, current terahertz systems are very bulky and expensive, sometimes even require cryogenic conditions. Silicon terahertz electronics now becomes very attractive, since it can achieve significantly lower cost and make portable consumer terahertz devices feasible. However, due to the limited device fmax and low breakdown voltage, signal generation and processing on silicon platform in this frequency range is challenging. This thesis aims to tackle these challenges and implement high-performance terahertz systems. First of all, the devices are investigated under the terahertz frequency range and optimum termination conditions for maximizing the efficacy of the devices is derived. Then, novel passive surrounding networks are designed to provide the devices with the optimal termination conditions to push the performances of the terahertz circuit blocks. Finally, the high-performance circuit blocks are used to build terahertz systems, and system-level innovations are also proposed to push the state of the art forward. In Chapter 2, using a device-centric bottom-up design method, a 210-GHz harmonic oscillator is designed. With the parasitic tuning mechanism, a wide frequency tuning range is achieved without using lossy varactors. A passive network based on the return-path gap coupler and self-feeding structure is also designed to provide optimal terminations for the active devices to maximize the harmonic power generation. Fabricated with a 0.13-um SiGe BiCMOS process, the oscillator is highly compact with a core size of only 290x95 um2. The output frequency can be tuned from 197.5 GHz to 219.7 GHz, which is around 10.6% compared to the center frequency. It also achieves a peak output power and dc-to-RF efficiency of 1.4 dBm and 2.4%, respectively. The measured output phase noise at 1 MHz offset is -87.5 dBc/Hz. The high power, wide tuning range, low phase noise, as well as compact size, make this oscillator very suitable for terahertz systems integration. In Chapter 3, the design of a 320-GHz fully-integrated terahertz imaging system is described. The system is composed of a phase-locked high-power transmitter and a coherent high-sensitivity subharmonic-mixing receiver, which are fabricated using a 0.13-um SiGe BiCMOS technology. To enhance the imaging sensitivity, a heterodyne coherent detection scheme is utilized. To obtain frequency coherency, fully-integrated phase-locked loops are implemented on both the transmitter and receiver chips. According to the measurement, consuming a total dc power of 605 mW, the transmitter chip achieves a peak radiated power of 2 mW and a peak EIRP of 21.1 dBm. The receiver chip achieves an equivalent incoherent responsivity of more than 7.26 MV/W and a sensitivity of 70.1 pW under an integration bandwidth of 1 kHz, with a total dc power consumption of 117 mW. The achieved sensitivity with this proposed coherent imaging transceiver is around ten times better compared with other state-of-the-art incoherent imagers. In Chapter 4, a spatial-orthogonal ASK transmitter architecture for high-speed terahertz wireless communication is presented. The self-sustaining oscillator-based transmitter architecture has an ultra-compact size and excellent power efficiency. With the proposed high-speed constant-load switch, significantly reduced modulation loss is achieved. Using polarization diversity and multi-level modulation, the throughput is largely enhanced. Array configuration is also adopted to enhance the link budget for higher signal quality and longer communication range. Fabricated in a 0.13-um SiGe BiCMOS technology, the 220-GHz transmitter prototype achieves an EIRP of 21 dBm and dc-to- THz-radiation efficiency of 0.7% in each spatial channel. A 24.4-Gb/s total data rate over a 10-cm communication range is demonstrated. With an external Teflon lens system, the demonstrated communication range is further extended to 52 cm. Compared with prior art, this prototype demonstrates much higher transmitter efficiency. In Chapter 5, an entirely-on-chip frequency-stabilization feedback mechanism is proposed, which avoids the use of both frequency dividers and off-chip references, achieving much lower system integration cost and power consumption. Using this mechanism, a 301.7-to-331.8-GHz source prototype is designed in a 0.13-um SiGe BiCMOS technology. According to the measurement, the source consumes a dc power of only 51.7 mW. The output phase noise is -71.1 and -75.2 dBc/Hz at 100 kHz and 1 MHz offset, respectively. A -13.9-dBm probed output power is also achieved. Overall, the prototype source demonstrates the largest output frequency range and lowest power consumption while achieving comparable phase noise and output power performances with respect to the state of the art. All the designs demonstrated in this thesis achieve good performances and push the state of the art forward, paving the way for implementation of more sophisticated terahertz circuits and systems for future applications

Passive und aktive Radio Frequency Identification Tags im 60-GHz-Band

Die Einführung des millimeter-Wellen-Bandes eröffnet neue Perspektiven für die Radio Frequency Identification (RFID) Kommunikationssysteme. Der Enwurf des Systems im 60-GHz-Band ermöglicht die Implementierung der On-Chip Antenne und darüber hinaus die Implementierung eines RFID-Tags auf einem einzigen Chip. Dennoch ist es aufgrund der gesetzlichen Beschränkung der effektiven isotropen Strahlungsleistung (EIRP) des Lesegeräts und der erhöhten Freiraum-Dielektrikumsverluste eine Herausforderung, eine zuverlässige Kommunikationsreichweite von mehreren Millimetern zu erreichen. Neue Lösungen sind für jeden Block sowohl im Lesegerät als auch im Single-Chip-Tag erforderlich. Obwohl das Lesegerät batteriebetrieben ist, ist es immer noch eine Herausforderung, die maximal zulässigen 20 dBm IERP des Lesersenders energieeffizient zu erzeugen. Darüber hinaus sollte der Empfänger einen ausreichenden Dynamikbereich haben, um das vom Tag kommende Signal zu erkennen. Auf der Tag-Seite sind die Hauptherausforderungen das Co-Design der effizienten On-Chip-Antennen-Implementierung, die hochempfindliche Gleichrichter-Implementierung und das Rückkommunikationskonzept. Diese Arbeit konzentriert sich auf die Machbarkeitsstudie des Single-Chip-RFID-Tags und die Implementierung im Millimeterwellenbereich. Es werden zwei Rückkommunikationskonzepte untersucht - Backscattering-Rückkommunikation und eine Kommunikation unter Verwendung von Ultra-Low-Power (ULP) Radios. Beide werden in einem 22 nm FDSOI Prozess auf einem Substrat mit geringem Widerstand implementiert. Beide Tags arbeiten mit einer Versorgungsspannung von 0,4 V, um die Kommunikationsreichweite zu maximieren. Die Link-Budgets sind so ausgelegt, dass sie die regulatorischen Beschränkungen einhalten. Die Auswahl des Technologieknotens wird begründet. Verschiedene Aspekte im Zusammenhang mit der Technologie werden diskutiert, wie z. B. Geräteleistung, passiver Qualitätsfaktor, Leistungsdichte der Kondensatoren. Der Backscattering RFID-Tag wird zuerst entworfen, da er eine relativ einfachere Topologie hat. Die Probleme der Gleichrichterempfindlichkeit im Rahmen des analogen Frontends, der On-Chip-Antenneneffizienz und der konjugierten Anpassung beider werden untersucht. Eine Kommunikationsreichweite von 5 mm wird angestrebt und realisiert. Um die Kommunikationsreichweite weiter zu erhöhen, wird in der zweiten Phase ein Tag mit einer aktiven Rückkommunikation implementiert. Hier wird die Gleichrichterempfindlichkeit weiter verbessert. Es wird ein 0,4V ULP Radio entworfen, das sich die Antenne mit dem Gleichrichter über einen Single-Pole- Double-Through (SPDT) Schalter teilt. Ein Abstand von 2 cm erwies sich als realisierbar, wobei die gesetzlichen Bestimmungen eingehalten und der dynamische Bereich des Leseempfängers nicht überschritten wurde. Es wird die höchste normalisierte Kommunikationsreichweite pro Leser-EIRP erreicht. Weitere Verbesserungsmöglichkeiten werden diskutiert

Analysis and Design of Silicon based Integrated Circuits for Radio Frequency Identification and Ranging Systems at 24GHz and 60GHz Frequency Bands

This scientific research work presents the analysis and design of radio frequency (RF) integrated circuits (ICs) designed for two cooperative RF identification (RFID) proof of concept systems. The first system concept is based on localizable and sensor-enabled superregenerative transponders (SRTs) interrogated using a 24GHz linear frequency modulated continuous wave (LFMCW) secondary radar. The second system concept focuses on low power components for a 60GHz continuous wave (CW) integrated single antenna frontend for interrogating close range passive backscatter transponders (PBTs). In the 24GHz localizable SRT based system, a LFMCW interrogating radar sends a RF chirp signal to interrogate SRTs based on custom superregenerative amplifier (SRA) ICs. The SRTs receive the chirp and transmit it back with phase coherent amplification. The distance to the SRTs are then estimated using the round trip time of flight method. Joint data transfer from the SRT to the interrogator is enabled by a novel SRA quench frequency shift keying (SQ-FSK) based low data rate simplex communication. The SRTs are also designed to be roll invariant using bandwidth enhanced microstrip patch antennas. Theoretical analysis is done to derive expressions as a function of system parameters including the minimum SRA gain required for attaining a defined range and equations for the maximum number of symbols that can be transmitted in data transfer mode. Analysis of the dependency of quench pulse characteristics during data transfer shows that the duty cycle has to be varied while keeping the on-time constant to reduce ranging errors. Also the worsening of ranging precision at longer distances is predicted based on the non-idealities resulting from LFMCWchirp quantization due to SRT characteristics and is corroborated by system level measurements. In order to prove the system concept and study the semiconductor technology dependent factors, variants of 24GHz SRA ICs are designed in a 130nm silicon germanium (SiGe) bipolar complementary metal oxide technology (BiCMOS) and a partially depleted silicon on insulator (SOI) technology. Among the SRA ICs designed, the SiGe-BiCMOS ICs feature a novel quench pulse shaping concept to simultaneously improve the output power and minimum detectable input power. A direct antenna drive SRA IC based on a novel stacked transistor cross-coupled oscillator topology employing this concept exhibit one of the best reported combinations of minimum detected input power level of −100 dBm and output power level of 5.6 dBm, post wirebonding. The SiGe stacked transistor with base feedback capacitance topology employed in this design is analyzed to derive parameters including the SRA loop gain for design optimization. Other theoretical contributions include the analysis of the novel integrated quench pulse shaping circuit and formulas derived for output voltage swing taking bondwire losses into account. Another SiGe design variant is the buffered antenna drive SRA IC having a measured minimum detected input power level better than −80 dBm, and an output power level greater than 3.2 dBm after wirebonding. The two inputs and outputs of this IC also enables the design of roll invariant SRTs. Laboratory based ranging experiments done to test the concepts and theoretical considerations show a maximum measured distance of 77m while transferring data at the rate of 0.5 symbols per second using SQ-FSK. For distances less than 10m, the characterized accuracy is better than 11 cm and the precision is better than 2.4 cm. The combination of the maximum range, precision and accuracy are one of the best reported among similar works in literature to the author’s knowledge. In the 60GHz close range CW interrogator based system, the RF frontend transmits a continuous wave signal through the transmit path of a quasi circulator (QC) interfaced to an antenna to interrogate a PBT. The backscatter is received using the same antenna interfaced to the QC. The received signal is then amplified and downconverted for further processing. To prove this concept, two optimized QC ICs and a downconversion mixer IC are designed in a 22nm fully depleted SOI technology. The first QC is the transmission lines based QC which consumes a power of 5.4mW, operates at a frequency range from 56GHz to 64GHz and occupies an area of 0.49mm2. The transmit path loss is 5.7 dB, receive path gain is 2 dB and the tunable transmit path to receive path isolation is between 20 dB and 32 dB. The second QC is based on lumped elements, and operates in a relatively narrow bandwidth from 59.6GHz to 61.5GHz, has a gain of 8.5 dB and provides a tunable isolation better than 20 dB between the transmit and receive paths. This QC design also occupies a small area of 0.34mm² while consuming 13.2mW power. The downconversion is realized using a novel folded switching stage down conversion mixer (FSSDM) topology optimized to achieve one of the best reported combination of maximum voltage conversion gain of 21.5 dB, a factor of 2.5 higher than reported state-of-the-art results, and low power consumption of 5.25mW. The design also employs a unique back-gate tunable intermediate frequency output stage using which a gain tuning range of 5.5 dB is attained. Theoretical analysis of the FSSDM topology is performed and equations for the RF input stage transconductance, bandwidth, voltage conversion gain and gain tuning are derived. A feasibility study for the components of the 60GHz integrated single antenna interrogator frontend is also performed using PBTs to prove the system design concept.:1 Introduction 1 1.1 Motivation and Related Work . . . . . . . . . . . . . . . . . . . . . 1 1.2 Scope and Functional Specifications . . . . . . . . . . . . . . . . . 4 1.3 Objectives and Structure . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Features and Fundamentals of RFIDs and Superregenerative Amplifiers 9 2.1 RFID Transponder Technology . . . . . . . . . . . . . . . . . . . . 9 2.1.1 Chipless RFID Transponders . . . . . . . . . . . . . . . . . 10 2.1.2 Semiconductor based RFID Transponders . . . . . . . . . . 11 2.1.2.1 Passive Transponders . . . . . . . . . . . . . . . . 11 2.1.2.2 Active Transponders . . . . . . . . . . . . . . . . . 13 2.2 RFID Interrogator Architectures . . . . . . . . . . . . . . . . . . . 18 2.2.1 Interferometer based Interrogator . . . . . . . . . . . . . . . 19 2.2.2 Ultra-wideband Interrogator . . . . . . . . . . . . . . . . . . 20 2.2.3 Continuous Wave Interrogators . . . . . . . . . . . . . . . . 21 2.3 Coupling Dependent Range and Operating Frequencies . . . . . . . 25 2.4 RFID Ranging Techniques . . . . . . . . . . . . . . . . . . . . . . . 28 2.4.0.1 Received Signal Strength based Ranging . . . . . 28 2.4.0.2 Phase based Ranging . . . . . . . . . . . . . . . . 30 2.4.0.3 Time based Ranging . . . . . . . . . . . . . . . . . 30 2.5 Architecture Selection for Proof of Concept Systems . . . . . . . . 32 2.6 Superregenerative Amplifier (SRA) . . . . . . . . . . . . . . . . . . 35 2.6.1 Fundamentals . . . . . . . . . . . . . . . . . . . . . . . . . . 35 2.6.2 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . 42 2.6.3 Frequency Domain Characteristics . . . . . . . . . . . . . . 45 2.7 Semiconductor Technologies for RFIC Design . . . . . . . . . . . . 48 2.7.1 Silicon Germanium BiCMOS . . . . . . . . . . . . . . . . . 48 2.7.2 Silicon-on-Insulator . . . . . . . . . . . . . . . . . . . . . . . 48 3 24GHz Superregenerative Transponder based Identification and Rang- ing System 51 3.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.1 SRT Identification and Ranging . . . . . . . . . . . . . . . . 51 3.1.2 Power Link Analysis . . . . . . . . . . . . . . . . . . . . . . 55 3.1.3 Non-idealities . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.4 SRA Quench Frequency Shift Keying for data transfer . . . 61 3.1.5 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 63 3.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.2.1 Low Power Direct Antenna Drive CMOS SRA IC . . . . . . 66 3.2.1.1 Circuit analysis and design . . . . . . . . . . . . . 66 3.2.1.2 Characterization . . . . . . . . . . . . . . . . . . . 69 3.2.2 Direct Antenna Drive SiGe SRA ICs . . . . . . . . . . . . . 71 3.2.2.1 Stacked Transistor Cross-coupled Quenchable Oscillator . . . . . . . . . . . . . . . . . . . . . . . . 72 3.2.2.1.1 Resonator . . . . . . . . . . . . . . . . . . 72 3.2.2.1.2 Output Network . . . . . . . . . . . . . . 75 3.2.2.1.3 Stacked Transistor Cross-coupled Pair and Loop Gain . . . . . . . . . . . . . . . . . 77 3.2.2.2 Quench Waveform Design . . . . . . . . . . . . . . 85 3.2.2.3 Characterization . . . . . . . . . . . . . . . . . . . 89 3.2.3 Antenna Diversity SiGe SRA IC with Integrated Quench Pulse Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . 91 3.2.3.1 Circuit Analysis and Design . . . . . . . . . . . . 91 3.2.3.1.1 Crosscoupled Pair and Sampling Current 94 3.2.3.1.2 Common Base Input Stage . . . . . . . . 95 3.2.3.1.3 Cascode Output Stage . . . . . . . . . . . 96 3.2.3.1.4 Quench Pulse Shaping Circuit . . . . . . 96 3.2.3.1.5 Power Gain . . . . . . . . . . . . . . . . . 99 3.2.3.2 Characterization . . . . . . . . . . . . . . . . . . . 102 3.2.4 Knowledge Gained . . . . . . . . . . . . . . . . . . . . . . . 103 3.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 106 3.3.1 Superregenerative Transponders . . . . . . . . . . . . . . . 106 3.3.1.1 Bandwidth Enhanced Microstrip Patch Antennas 108 3.3.2 FMCW Radar Interrogator . . . . . . . . . . . . . . . . . . 114 3.3.3 Chirp Z-transform Based Data Analysis . . . . . . . . . . . 116 4 60GHz Single Antenna RFID Interrogator based Identification System 121 4.1 System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 4.2 RFIC Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1 Quasi-circulator ICs . . . . . . . . . . . . . . . . . . . . . . 125 4.2.1.1 Transmission Lines based Quasi-Circulator IC . . 126 4.2.1.2 Lumped Elements WPD based Quasi-Circulator . 130 4.2.1.3 Characterization . . . . . . . . . . . . . . . . . . . 134 4.2.1.4 Knowledge Gained . . . . . . . . . . . . . . . . . . 135 4.2.2 Folded Switching Stage Downconversion Mixer IC . . . . . 138 4.2.2.1 FSSDM Circuit Design . . . . . . . . . . . . . . . 138 4.2.2.2 Cascode Transconductance Stage . . . . . . . . . . 138 4.2.2.3 Folded Switching Stage with LC DC Feed . . . . . 142 4.2.2.4 LO Balun . . . . . . . . . . . . . . . . . . . . . . . 145 4.2.2.5 Backgate Tunable IF Stage and Offset Correction 146 4.2.2.6 Voltage Conversion Gain . . . . . . . . . . . . . . 147 4.2.2.7 Characterization . . . . . . . . . . . . . . . . . . . 150 4.2.2.8 Knowledge Gained . . . . . . . . . . . . . . . . . . 151 4.3 Proof of Principle System Implementation . . . . . . . . . . . . . . 154 5 Experimental Tests 157 5.1 24GHz System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 5.1.1 Ranging Experiments . . . . . . . . . . . . . . . . . . . . . 157 5.1.2 Roll Invariance Experiments . . . . . . . . . . . . . . . . . . 158 5.1.3 Joint Ranging and Data Transfer Experiments . . . . . . . 158 5.2 60GHz System Detection Experiments . . . . . . . . . . . . . . . . 165 6 Summary and Future Work 167 Appendices 171 A Derivation of Parameters for CB Amplifier with Base Feedback Capac- itance 173 B Definitions 177 C 24GHz Experiment Setups 179 D 60 GHz Experiment Setups 183 References 185 List of Original Publications 203 List of Abbreviations 207 List of Symbols 213 List of Figures 215 List of Tables 223 Curriculum Vitae 22

Collective analog bioelectronic computation

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2009.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Cataloged from student submitted PDF version of thesis.Includes bibliographical references (p. 677-710).In this thesis, I present two examples of fast-and-highly-parallel analog computation inspired by architectures in biology. The first example, an RF cochlea, maps the partial differential equations that describe fluid-membrane-hair-cell wave propagation in the biological cochlea to an equivalent inductor-capacitor-transistor integrated circuit. It allows ultra-broadband spectrum analysis of RF signals to be performed in a rapid low-power fashion, thus enabling applications for universal or software radio. The second example exploits detailed similarities between the equations that describe chemical-reaction dynamics and the equations that describe subthreshold current flow in transistors to create fast-and-highly-parallel integrated-circuit models of protein-protein and gene-protein networks inside a cell. Due to a natural mapping between the Poisson statistics of molecular flows in a chemical reaction and Poisson statistics of electronic current flow in a transistor, stochastic effects are automatically incorporated into the circuit architecture, allowing highly computationally intensive stochastic simulations of large-scale biochemical reaction networks to be performed rapidly. I show that the exponentially tapered transmission-line architecture of the mammalian cochlea performs constant-fractional-bandwidth spectrum analysis with O(N) expenditure of both analysis time and hardware, where N is the number of analyzed frequency bins. This is the best known performance of any spectrum-analysis architecture, including the constant-resolution Fast Fourier Transform (FFT), which scales as O(N logN), or a constant-fractional-bandwidth filterbank, which scales as O (N2).(cont.) The RF cochlea uses this bio-inspired architecture to perform real-time, on-chip spectrum analysis at radio frequencies. I demonstrate two cochlea chips, implemented in standard 0.13m CMOS technology, that decompose the RF spectrum from 600MHz to 8GHz into 50 log-spaced channels, consume < 300mW of power, and possess 70dB of dynamic range. The real-time spectrum analysis capabilities of my chips make them uniquely suitable for ultra-broadband universal or software radio receivers of the future. I show that the protein-protein and gene-protein chips that I have built are particularly suitable for simulation, parameter discovery and sensitivity analysis of interaction networks in cell biology, such as signaling, metabolic, and gene regulation pathways. Importantly, the chips carry out massively parallel computations, resulting in simulation times that are independent of model complexity, i.e., O(1). They also automatically model stochastic effects, which are of importance in many biological systems, but are numerically stiff and simulate slowly on digital computers. Currently, non-fundamental data-acquisition limitations show that my proof-of-concept chips simulate small-scale biochemical reaction networks at least 100 times faster than modern desktop machines. It should be possible to get 103 to 106 simulation speedups of genome-scale and organ-scale intracellular and extracellular biochemical reaction networks with improved versions of my chips. Such chips could be important both as analysis tools in systems biology and design tools in synthetic biology.by Soumyajit Mandal.Ph.D