A Noise-Shifting Differential Colpitts VCO

A novel noise-shifting differential Colpitts VCO is presented. It uses current switching to lower phase noise by cyclostationary noise alignment and improve the start-up condition. A design strategy is also devised to enhance the phase noise performance of quadrature coupled oscillators. Two integrated VCOs are presented as design examples

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 µW. PSpice simulation results using the 0.18 µm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system

Design and characterization of downconversion mixers and the on-chip calibration techniques for monolithic direct conversion radio receivers

This thesis consists of eight publications and an overview of the research topic, which is also a summary of the work. The research described in this thesis is focused on the design of downconversion mixers and direct conversion radio receivers for UTRA/FDD WCDMA and GSM standards. The main interest of the work is in the 1-3 GHz frequency range and in the Silicon and Silicon-Germanium BiCMOS technologies. The RF front-end, and especially the mixer, limits the performance of direct conversion architecture. The most stringent problems are involved in the second-order distortion in mixers to which special attention has been given. The work introduces calibration techniques to overcome these problems. Some design considerations for front-end radio receivers are also given through a mixer-centric approach. The work summarizes the design of several downconversion mixers. Three of the implemented mixers are integrated as the downconversion stages of larger direct conversion receiver chips. One is realized together with the LNA as an RF front-end. Also, some stand-alone structures have been characterized. Two of the mixers that are integrated together with whole analog receivers include calibration structures to improve the second-order intermodulation rejection. A theoretical mismatch analysis of the second-order distortion in the mixers is also presented in this thesis. It gives a comprehensive illustration of the second-order distortion in mixers. It also gives the relationships between the dc-offsets and high IIP2. In addition, circuit and layout techniques to improve the LO-to-RF isolation are discussed. The presented work provides insight into how the mixer immunity against the second-order distortion can be improved. The implemented calibration structures show promising performance. On the basis of these results, several methods of detecting the distortion on-chip and the possibilities of integrating the automatic on-chip calibration procedures to produce a repeatable and well-predictable receiver IIP2 are presented.reviewe

Silicon Germanium BiCMOS Integrated Circuits for Scalable Cryogenic Sensing Applications

This dissertation is focused on an investigation of BiCMOS cryogenic low noise amplifiers (LNAs) based on Silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) for simultaneous low noise and low power design and also taking advantage of CMOS circuitry for adding flexibility to the LNA design. Cryogenic LNAs\u27 scalability challenges are discussed and addressed in the dissertation. To achieve that, first, HBTs of three state-of-the-art technologies are characterized and modeled at cryogenic temperature. It is shown that SiGe HBT provides a promising compromise of noise temperature, power consumption, and bandwidth. Moreover, a scalable on-chip approach is proposed and verified for biasing of SiGe HBTs based LNAs. Finally, the first cryogenic re-configurable LNA is designed, implemented, and measured

Développement d'une architecture innovante de récepteur radar à 77 GHz et démonstration en CMOS 28 nm FDSOI

Grâce à sa capacité à détecter des cibles éloignées malgré une mauvaise visibilité, le radar automobile à 77 GHz joue un rôle important dans l'aide à la conduite. L'utilisation des fréquences millimétriques offre une bonne résolution et une importante capacité d'intégration des circuits. C'est aussi un défi car il faut satisfaire un cahier des charges exigeant sur le bruit et la linéarité du récepteur. Les technologies SiGe BiCMOS ont été les premières utilisées pour la conception de récepteurs radar à 77 GHz. De bons résultats ont été obtenus en se basant sur des architectures utilisant des mélangeurs actifs. Cependant l'utilisation des technologie BiCMOS se traduisait par une consommation élevée, une faible capacité d'intégration et des coûts de production importants. Récemment, l'intégration des procédés CMOS menant à l'augmentation des fréquences de transition rend ces technologies plus attractives pour les applications nécessitant un faible coût et la cointégration de plusieurs fonctions au sein d'une même puce. La littérature sur les récepteurs radars en technologie CMOS à 77 GHz montre que les architectures inspirées par les technologies BiCMOS ne sont pas pertinentes pour cette application. Le but de cette thèse et de montrer que l'utilisation de techniques propres aux technologie CMOS comme l'échantillonnage et l'utilisation de portes logiques permet d'obtenir de très bonnes performances. Dans ce travail, deux nouvelles architectures de récepteurs radars basées sur le principe d'échantillonnage sont proposées. La première architecture est basée sur un mélangeur passif échantillonné qui permet d'obtenir un très bon compromis bruit/linéarité. La seconde exploite les propriétés des mélangeurs sous-échantillonnés afin utiliser une fréquence d'OL trois fois inférieure à la fréquence RF offrant ainsi de très intéressantes simplifications au niveau de la chaîne de distribution du signal d'OL du récepteur. Le contexte de cette étude est expliqué dans le 1er chapitre qui présente les exigences de conception liées à l'application radar et fourni une analyse de l'état de l'art des récepteurs à 77 GHZ. Le chapitre suivant décrit le principe de fonctionnement et l'implémentation d'un mélangeur échantillonné à 77 GHz en technologie CMOS 28- nm FDSOI. Une topologie de mélangeur sous-échantillonné utilisant une fréquence d'OL de 26 GHz pour convertir des signaux RF autour de 77 GHz est ensuite détaillée dans le chapitre 3. Le chapitre 4 conclut cette étude en détaillant l'intégration des mélangeurs étudiés dans les chapitres précédents avec un amplificateur faible bruit dans différents récepteurs radars. Ces architectures de récepteurs basées sur l'échantillonnage sont ensuite comparées entre elles et avec l'état de l'art montrant ainsi leurs avantages et inconvénients. Les résultats de cette comparaison confirment l'intérêt des techniques d'échantillonnage pour la conversion de fréquence dans le cadre de l'application radar.With its ability to detect distant targets under harsh visibility conditions, the 77 GHz automotive radar plays a key role in driving safety. Using mm-wave frequencies allow a good range resolution, a better circuit integration and a wide modulation bandwidth. This is also a challenge for circuit designers who must fulfill stringent requirements especially on the receiver front-end. First 77 GHz radar receivers were manufactured with SiGe BiCMOS processes benefiting from the high transition frequency and high breakdown voltage of Hetero-junction Bipolar Transistors (HBT). Good results have been achieved with active-mixer-based architectures, but these technologies suffer from high power consumptions, limited integration capacity and large production cost. More recently, the scaling down of CMOS processes (coming together with the increase of the transition frequency of the transistors) makes CMOS a good candidate for 77 GHz circuit design, especially when cost target requires single chip solutions. The literature related to CMOS radar receivers highlights that receivers based on BiCMOS architectures generally show poor performances. The aim of this work is to demonstrate that using CMOS specific technics such as sampling and the use of high-speed digital gates should enhance the performance of the receivers. In this work, two innovative radar receiver architectures based on the sampling principle are proposed. The first one shows that this principle can be extended to millimeter wave frequencies to benefit from a very good noise/linearity trade-off. While the second one uses this principle to converts a 77 GHz RF signal by using a 26 GHz LO frequency thus simplifying the LO distribution chain of the receiver. The background of this study is introduced in the chapter 1 presenting the design trade-off related to the 77 GHz radar receiver and provides a review of the existing solutions. The following chapter describes the sampling mixer principle and the implementation of a 77 GHz sampling mixer in 28-nm FDSOI CMOS technology. Then, a sub- sampling mixer topology allowing to convert an RF signal around 77 GHz using a 26 GHz LO frequency is detailed in the chapter 3. The chapter 4 draws the conclusion of this study by showing the implementation of the two proposed sampling-based mixers with a low noise amplifier in 77 GHz front ends. These receiver architectures are compared with the state of the art highlighting the strengths and weaknesses of the proposed solutions. The results of this study demonstrates that using sampling for down conversion can be convenient to address millimeter-wave frequency applications

Millimeter-Wave Super-Regenerative Receivers for Wireless Communication and Radar

Today’s world is becoming increasingly automated and interconnected with billions of smart devices coming online, leading to a steep rise in energy consumption from small microelectronics. This coincides with an urgent push to transform global energy production to green energies, causing disruptions and energy shortages, and making the case for efficient energy use ever more pressing. Two major areas where high growth is expected are the fields of wireless communication and radar sensors. Millimeter-wave frequency bands are planned for fifth-generation (5G) and sixth-generation (6G) cellular communication standards, as well as automotive frequency-modulated continuous wave (FMCW) radar systems for driving assistance and automation. Fast silicon-based technologies enable these advances by operating at high maximum frequencies, such as the silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) technologies. However, even the fastest transistors suffer from low and energy expensive gains at millimeter-wave frequencies. Rather than incremental improvements in circuit efficiency using conventional approaches, a disruptive revolution for green microelectronics could be enabled by exploring the low-power benefits of the super-regenerative receiver for some applications. The super-regenerative receiver uses a regenerative oscillator circuit to increase the gain by positive feedback, through coupling energy from the output back into the input. Careful bias and control of the circuit enables a very large gain from a small number of transistors and a very low energy dissipation. Thus, the super-regenerative oscillator could be used to replace amplifier circuits in high data rate wireless communication systems, or as active reflectors to increase the range of FMCW radar systems, greatly reducing the power consumption. The work in this thesis presents fundamental scientific research into the topic of energy-efficient millimeter-wave super-regenerative receivers for use in civilian wireless communication and radar applications. This research work covers the theory, analysis, and simulations, all the way up to the proof of concept, hardware realization, and experimental characterization. Analysis and modeling of regenerative oscillator circuits is presented and used to improve the understanding of the circuit operation, as well as design goals according to the specific application needs. Integrated circuits are investigated and characterized as a proof of concept for a high data rate wireless communication system operating between 140–220 GHz, and an automotive radar system operating at 60 GHz. Amplitude and phase regeneration capabilities for complex modulation are investigated, and principles for spectrum characterization are derived. The circuits are designed and fabricated in a 130 nm SiGe HBT technology, combining bipolar and complementary metal-oxide semiconductor (BiCMOS) transistors. To prove the feasibility of the research concepts, the work achieves a wireless communication link at 16 Gbit/s over 20 cm distance with quadrature amplitude modulation (QAM), which is a world record for the highest data rate ever reported in super-regenerative circuits. This was powered by a super-regenerative oscillator circuit operating at 180 GHz and providing 58 dB of gain. Energy efficiency is also considerably high, drawing 8.8 mW of dc power consumption, which corresponds to a highly efficient 0.6 pJ/bit. Packaging and module integration innovations were implemented for the system experiments, and additional broadband circuits were investigated to generate custom quench waveforms to further enhance the data rate. For radar active reflectors, a regenerative gain of 80 dB is achieved at 60 GHz from a single circuit, which is the best in its frequency range, despite a low dc power consumption of 25 mW