Passive Mixer-based UWB Receiver with Low Loss, High Linearity and Noise-cancelling for Medical Applications

A double balanced passive mixer-based receiver operating in the 3-5 GHz UWB for medical applications is described in this paper. The receiver front-end circuit is composed of an inductorless low noise amplifier (LNA) followed by a fully differential voltage-driven double-balanced passive mixer. A duty cycle of 25% was chosen to eliminate overlap between LO signals, thereby improving receiver linearity. The LNA realizes a gain of 25.3 dB and a noise figure of 2.9 dB. The proposed receiver achieves an IIP3 of 3.14 dBm, an IIP2 of 17.5 dBm and an input return loss (S11) below -12.5dB. Designed in 0.18μm CMOS technology, the proposed mixer consumes 0.72pW from a 1.8V power supply. The designed receiver demonstrated a good ports isolation performance with LO_IF isolation of 60dB and RF_IF isolation of 78dB

High frequency of low noise amplifier architecture for WiMAX application: A review

The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

A Millimeter-Wave Coexistent RFIC Receiver Architecture in 0.18-µm SiGe BiCMOS for Radar and Communication Systems

Innovative circuit architectures and techniques to enhance the performance of several key BiCMOS RFIC building blocks applied in radar and wireless communication systems operating at the millimeter-wave frequencies are addressed in this dissertation. The former encapsulates the development of an advanced, low-cost and miniature millimeter-wave coexistent current mode direct conversion receiver for short-range, high-resolution radar and high data rate communication systems. A new class of broadband low power consumption active balun-LNA consisting of two common emitters amplifiers mutually coupled thru an AC stacked transformer for power saving and gain boosting. The active balun-LNA exhibits new high linearity technique using a constant gm cell transconductance independent of input-outputs variations based on equal emitters’ area ratios. A novel multi-stages active balun-LNA with innovative technique to mitigate amplitude and phase imbalances is proposed. The new multi-stages balun-LNA technique consists of distributed feed-forward averaging recycles correction for amplitude and phase errors and is insensitive to unequal paths parasitic from input to outputs. The distributed averaging recycles correction technique resolves the amplitude and phase errors residuals in a multi-iterative process. The new multi-stages balun-LNA averaging correction technique is frequency independent and can perform amplitude and phase calibrations without relying on passive lumped elements for compensation. The multi-stage balun-LNA exhibits excellent performance from 10 to 50 GHz with amplitude and phase mismatches less than 0.7 dB and 2.86º, respectively. Furthermore, the new multi-stages balun-LNA operates in current mode and shows high linearity with low power consumption. The unique balun-LNA design can operates well into mm-wave regions and is an integral block of the mm-wave radar and communication systems. The integration of several RFIC blocks constitutes the broadband millimeter-wave coexistent current mode direct conversion receiver architecture operating from 22- 44 GHz. The system and architectural level analysis provide a unique understanding into the receiver characteristics and design trade-offs. The RF front-end is based on the broadband multi-stages active balun-LNA coupled into a fully balanced passive mixer with an all-pass in-phase/quadrature phase generator. The trans-impedance amplifier converts the input signal current into a voltage gain at the outputs. Simultaneously, the high power input signal current is channelized into an anti-aliasing filter with 20 dB rejection for out of band interferers. In addition, the dissertation demonstrates a wide dynamic range system with small die area, cost effective and very low power consumption

Low-power CMOS front-ends for wireless personal area networks

The potential of implementing subthreshold radio frequency circuits in deep sub-micron CMOS technology was investigated for developing low-power front-ends for wireless personal area network (WPAN) applications. It was found that the higher transconductance to bias current ratio in weak inversion could be exploited in developing low-power wireless front-ends, if circuit techniques are employed to mitigate the higher device noise in subthreshold region. The first fully integrated subthreshold low noise amplifier was demonstrated in the GHz frequency range requiring only 260 μW of power consumption. Novel subthreshold variable gain stages and down-conversion mixers were developed. A 2.4 GHz receiver, consuming 540 μW of power, was implemented using a new subthreshold mixer by replacing the conventional active low noise amplifier by a series-resonant passive network that provides both input matching and voltage amplification. The first fully monolithic subthreshold CMOS receiver was also implemented with integrated subthreshold quadrature LO (Local Oscillator) chain for 2.4 GHz WPAN applications. Subthreshold operation, passive voltage amplification, and various low-power circuit techniques such as current reuse, stacking, and differential cross coupling were combined to lower the total power consumption to 2.6 mW. Extremely compact resistive feedback CMOS low noise amplifiers were presented as a cost-effective alternative to narrow band LNAs using high-Q inductors. Techniques to improve linearity and reduce power consumption were presented. The combination of high linearity, low noise figure, high broadband gain, extremely small die area and low power consumption made the proposed LNA architecture a compelling choice for many wireless applications.Ph.D.Committee Chair: Laskar, Joy; Committee Member: Chakraborty, Sudipto; Committee Member: Chang, Jae Joon; Committee Member: Divan, Deepakraj; Committee Member: Kornegay, Kevin; Committee Member: Tentzeris, Emmanoui

HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING

In future, the radar/satellite wireless communication devices must support multiple standards and should be designed in the form of system-on-chip (SoC) so that a significant reduction happen on cost, area, pins, and power etc. However, in such device, the design of a fully on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously becomes a multifold complex problem. Further, the inherent high-power out-of-band (OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate the receiver. Therefore, the proper blocker rejection techniques need to be incorporated. The primary focus of this research work is the development of a CMOS high-performance low noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further, the various reconfigurable mixer architectures are proposed for performance adaptability of a wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced fully differential receiver is proposed. The receiver composed of a composite transistor pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm, occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary subthreshold receiver is proposed to estimate the out of blocker power. As a redundant block in the system, the cost and power minimization of the auxiliary receiver are achieved via subthreshold circuit design techniques and implementing the design in higher technology node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various viii reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance according to the requirement of the selected communication standard. The down conversion mixers configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept, the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of -11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz for active/passive case respectively

A robust 2.4 GHz time-of-arrival based ranging system with sub-meter accuracy: feasibility study and realization of low power CMOS receiver

Draadloze sensornetwerken worden meer en meer aangewend om verschillende soorten informatie te verzamelen. De locatie, waar deze informatie verzameld is, is een belangerijke eigenschap en voor sommige toepassingen, zoals het volgen van personen of goederen, zelfs de meest belangrijke en mogelijkmakende factor. Om de positie van een sensor te bepalen, is een technologie nodig die de afstand tot een gekend referentiepunt schat. Door verschillende afstandsmetingen te combineren, is het mogelijk de absolute locatie van de node te berekenen

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic

Passive and active circuits in cmos technology for rf, microwave and millimeter wave applications

The permeation of CMOS technology to radio frequencies and beyond has fuelled an urgent need for a diverse array of passive and active circuits that address the challenges of rapidly emerging wireless applications. While traditional analog based design approaches satisfy some applications, the stringent requirements of newly emerging applications cannot necessarily be addressed by existing design ideas and compel designers to pursue alternatives. One such alternative, an amalgamation of microwave and analog design techniques, is pursued in this work. A number of passive and active circuits have been designed using a combination of microwave and analog design techniques. For passives, the most crucial challenge to their CMOS implementation is identified as their large dimensions that are not compatible with CMOS technology. To address this issue, several design techniques – including multi-layered design and slow wave structures – are proposed and demonstrated through experimental results after being suitably tailored for CMOS technology. A number of novel passive structures - including a compact 10 GHz hairpin resonator, a broadband, low loss 25-35 GHz Lange coupler, a 25-35 GHz thin film microstrip (TFMS) ring hybrid, an array of 0.8 nH and 0.4 nH multi-layered high self resonant frequency (SRF) inductors are proposed, designed and experimentally verified. A number of active circuits are also designed and notable experimental results are presented. These include 3-10 GHz and DC-20 GHz distributed low noise amplifiers (LNA), a dual wideband Low noise amplifier and 15 GHz distributed voltage controlled oscillators (DVCO). Distributed amplifiers are identified as particularly effective in the development of wideband receiver front end sub-systems due to their gain flatness, excellent matching and high linearity. The most important challenge to the implementation of distributed amplifiers in CMOS RFICs is identified as the issue of their miniaturization. This problem is solved by using integrated multi-layered inductors instead of transmission lines to achieve over 90% size compression compared to earlier CMOS implementations. Finally, a dual wideband receiver front end sub-system is designed employing the miniaturized distributed amplifier with resonant loads and integrated with a double balanced Gilbert cell mixer to perform dual band operation. The receiver front end measured results show 15 dB conversion gain, and a 1-dB compression point of -4.1 dBm in the centre of band 1 (from 3.1 to 5.0 GHz) and -5.2 dBm in the centre of band 2 (from 5.8 to 8 GHz) with input return loss less than 10 dB throughout the two bands of operation