Memcapacitive Devices in Logic and Crossbar Applications

Over the last decade, memristive devices have been widely adopted in computing for various conventional and unconventional applications. While the integration density, memory property, and nonlinear characteristics have many benefits, reducing the energy consumption is limited by the resistive nature of the devices. Memcapacitors would address that limitation while still having all the benefits of memristors. Recent work has shown that with adjusted parameters during the fabrication process, a metal-oxide device can indeed exhibit a memcapacitive behavior. We introduce novel memcapacitive logic gates and memcapacitive crossbar classifiers as a proof of concept that such applications can outperform memristor-based architectures. The results illustrate that, compared to memristive logic gates, our memcapacitive gates consume about 7x less power. The memcapacitive crossbar classifier achieves similar classification performance but reduces the power consumption by a factor of about 1,500x for the MNIST dataset and a factor of about 1,000x for the CIFAR-10 dataset compared to a memristive crossbar. Our simulation results demonstrate that memcapacitive devices have great potential for both Boolean logic and analog low-power applications

Modeling and design of memristor-based fuzzy systems

The incessant down scaling of CMOS technology has been the main driving force for the semiconductor industry over the past decades. Yet, as process variations and leakage current continue to exhibit more pronounced effect with every technology node, this down scaling paradigm is expected to saturate in the few coming years. This prospect has led the research community to seek new technologies to surpass those challenges. Amongst the promising candidates is the memristor technology recently characterized by HP Labs. The miniaturized features and the peculiar behavior exhibited by the memsitor make it very well suited in some applications. For instance, memrsitors are used as memory cells in state-of-the-art memories known as Resistive RAMs in which the non-volatility of the memristor is exploited. The programmable nature of the memristor has made it a powerful candidate in neuromorphic and fuzzy systems that, in essence, go beyond the classical Von Neumann computing paradigm. In such systems, ideas from Artificial Intelligence, that for so long have been implemented on the software level, are implemented as electronic circuitry which renders benefits such as compact area and reduced power consumption. This work focuses on memrsitor-based Fuzzy applications. First, memristor-based Min-Max circuit used in the Fuzzy Inference engine is analyzed. It is proven that memrsitor-based Min-Max circuits can be extended to an arbitrary number of inputs ‘N’ under the proper design constraints. In addition, the effect of the memristor threshold is analyzed and a closed form expression is derived. It is shown that, for a given memristor with a specific OFF resistance and threshold current, there is a trade-off between the size and the resolution of the circuit. Then, a memrsitor-based Defuzzifier circuit is proposed. A major challenge in Defuzzifiers is their area occupancy due to the use of Multiplier and Divider circuits. In this design, the memrsitor analog programmability is leveraged to reduce the multiplication operation into simple Ohm’s Law which alleviates the need for dedicated hardware for multiplier circuit and, accordingly, reduces the area occupancy

VLSI Design

This book provides some recent advances in design nanometer VLSI chips. The selected topics try to present some open problems and challenges with important topics ranging from design tools, new post-silicon devices, GPU-based parallel computing, emerging 3D integration, and antenna design. The book consists of two parts, with chapters such as: VLSI design for multi-sensor smart systems on a chip, Three-dimensional integrated circuits design for thousand-core processors, Parallel symbolic analysis of large analog circuits on GPU platforms, Algorithms for CAD tools VLSI design, A multilevel memetic algorithm for large SAT-encoded problems, etc

Memristor-Based Digital Systems Design and Architectures

Memristor is considered as a suitable alternative solution to resolve the scaling limitation of CMOS technology. In recent years, the use of memristors in circuits design has rapidly increased and attracted researcher’s interest. Advances have been made to both size and complexity of memristor designs. The development of CMOS transistors shows major concerns, such as, increased leakage power, reduced reliability, and high fabrication cost. These factors have affected chip manufacturing process and functionality severely. Therefore, the demand for new devices is increasing. Memristor, is considered as one of the key element in memory and information processing design due to its small size, long-term data storage, low power, and CMOS compatibility. The main objective in this research is to design memristor-based arithmetic circuits and to overcome some of the Memristor based logic design issues. In this thesis, a fast, low area and low power hybrid CMOS memristor based digital circuit design were implemented. Small and large-scale memristor based digital circuits are implemented and provided a solutions for overcoming the memristor degradation and fan-out challenges. As an example, a 4- bit LFSR has been implemented by using MRL scheme with 64 CMOS devices and 64 memristors. The proposed design is more efficient in terms of the area when compared with CMOS- based LFSR circuits. The simulation results proves the functionality of the design. This approach presents acceptable speed in comparison with CMOS-based design and it is faster than IMPLY-based memrisitive LFSR. The propped LFSR has 841 ps de-lay. Furthermore, the proposed design has a significant power reduction of over 66% less than CMOS-based approach. This thesis proposes implementation of memristive 2-D median filter and extends previously published works on memristive Filter design to include this emerging technology characteristics in image processing. The proposed circuit was designed based on Pt/TaOx/Ta redox-based device and Memristor Ratioed Logic (MRL). The proposed filter is designed in Cadence and the memristive median approved tested circuit is translated to Verilog-XL as a behavioral model. Different 512 _ 512 pixels input images contain salt and pepper noise with various noise density ratios are applied to the proposed median filter and the design successfully has substantially removed the noise. The implementation results in comparison with the conventional filters, it gives better Peak Signal to Noise Ratio (PSNR) and Mean Absolute Error (MAE) for different images with different noise density ratios while it saves more area as compared to CMOS-based design. This dissertation proposes a comprehensive framework for design, mapping and synthesis of large-scale memristor-CMOS circuits. This framework provides a synthesis approach that can be applied to all memristor-based digital logic designs. In particular, it is a proposal for a characterization methodology of memristor-based logic cells to generate a standard cell library for large scale simulation. The proposed framework is implemented in the Cadence Virtuoso schematic-level environment and was veri_ed with Verilog-XL, MATLAB, and the Electronic Design Automation (EDA) Synopses compiler after being translated to the behavioral level. The proposed method can be applied to implement any digital logic design. The frame work is deployed for design of the memristor-based parallel 8-bit adder/subtractor and a 2-D memristive-based median filter

Power Control for Crossbar-based Input-Queued Switches

Abstract—We consider an N ×N input-queued switch with a crossbarbased switching fabric implemented on a single chip. The power consumption produced by the crossbar chip and due to the data transfer grows as NR 3, where R is the maximum bit rate. Thus, at increasing bit rate, power dissipation is becoming more and more challenging, limiting the crossbar scalability for high performance switches. We propose to exploit Dynamic Voltage and Frequency Scaling (DVFS) techniques to control packet transmissions through each crosspoint of the switching fabric. Our power control operates independently of the packet scheduler and exploits the knowledge of a traffic matrix obtained by on-line measurements. We propose a family of control algorithms to reduce the power consumption. The algorithms are particularly efficient in non-overloaded conditions. The actual potential of the proposed approach is also evaluated on a real design case synthesized on a 90 nm CMOS technology. Index Terms—Input queued switch, power control, dynamic voltage frequency scaling.

Confession Session: Learning from Others Mistakes

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