Development of a solid state amplifier for the 3rd harmonic cavity for ALBA synchrotron light source

In Synchrotron Light Source facilities with high energy and low emittance electron beams different techniques for improving the quality of the synchrotron light for the users are applied. With this aim ALBA, the Spanish 3rd generation Synchrotron Light Source, is developing a 3rd Harmonic radiofrequency (RF) system as a system additional to the main RF system of the storage ring. This system will consist of four normal conducting active cavities at 1.5 GHz that will provide the required 1.1 MV accelerating voltage to the electron beam and will be fed by four 20 kW power transmitters. This power will be generated by modular Solid State Power Amplifiers (SSPAs) in a continuous wave mode at 1.5 GHz. On the basis of preliminary studies it has been decided that the architecture of each 20 kW power transmitter is a tree diagram made up of primary 1 kW SSPA modules connected in parallel in a combination array. The present PhD thesis is devoted to the design, building and evaluation of a prototype of the 1 kW SSPA module formed four 250 W primary power amplifier modules. Accordingly, all subsystems, namely input and output matching networks of the 250 W primary module, and a four-way power splitter, a four-way power combiner and a novel directivity compensated directional coupler for the non-invasive power monitoring of the 1 kW power amplifier were also designed and their prototypes were tested. A final evaluation of the combined 1 kW SSPA prototype module was successfully carried out and has shown good performance.En las instalaciones de tipo Fuentes de luz de sincrotrón de haz de electrones de alta energía y baja emitancia se aplican diferentes técnicas de mejora de la calidad de la luz de sincrotrón. Con este objetivo, el ALBA, la fuente española de luz de sincrotrón de la tercera generación, está desarrollando un sistema de radiofrecuencia (RF) de la 3ª Harmónica como un sistema adicional al sistema de RF principal del anillo de almacenamiento. Este sistema consistirá de cuatro cavidades activas de conductividad normal de frecuencia 1,5 GHz que suministrarán un voltaje acelerador de 1.1 MV necesario para el haz de electrones y que serán alimentadas por cuatro transmisores de potencia de 20 kW. Esta potencia será generada en modo de onda continua a frecuencia 1.5 GHz por amplificadores de potencia de estado sólido (APES) de estructura modular. A partir de unos estudios preliminares se ha decidido que la arquitectura de cada transmisor de potencia de 20 kW es de tipo diagrama de árbol que consiste de APES primarios de potencia 1 kW conectados en paralelo formando una matriz de combinación. El tema de la presente tesis es el diseño, la construcción y la caracterización de un prototipo del módulo de APES de potencia 1 kW formado por cuatro amplificadores primarios de 250 W de potencia. También, todos subsistemas, concretamente los circuitos de adaptación de entrada y de salida del módulo primario de 250 kW, así como un divisor de cuatro salidas, un combinador de cuatro entradas y un acoplador direccional con una nova solución de compensación de directividad para una monitorización no invasiva han sido diseñados y sus prototipos han sido testeados. La evaluación final de funcionamiento del APES de 1 kW de potencia ha sido realizada con éxito y ha demostrado su buen rendimiento.Postprint (published version

Development of a solid state amplifier for the 3rd harmonic cavity for ALBA synchrotron light source

In Synchrotron Light Source facilities with high energy and low emittance electron beams different techniques for improving the quality of the synchrotron light for the users are applied. With this aim ALBA, the Spanish 3rd generation Synchrotron Light Source, is developing a 3rd Harmonic radiofrequency (RF) system as a system additional to the main RF system of the storage ring. This system will consist of four normal conducting active cavities at 1.5 GHz that will provide the required 1.1 MV accelerating voltage to the electron beam and will be fed by four 20 kW power transmitters. This power will be generated by modular Solid State Power Amplifiers (SSPAs) in a continuous wave mode at 1.5 GHz. On the basis of preliminary studies it has been decided that the architecture of each 20 kW power transmitter is a tree diagram made up of primary 1 kW SSPA modules connected in parallel in a combination array. The present PhD thesis is devoted to the design, building and evaluation of a prototype of the 1 kW SSPA module formed four 250 W primary power amplifier modules. Accordingly, all subsystems, namely input and output matching networks of the 250 W primary module, and a four-way power splitter, a four-way power combiner and a novel directivity compensated directional coupler for the non-invasive power monitoring of the 1 kW power amplifier were also designed and their prototypes were tested. A final evaluation of the combined 1 kW SSPA prototype module was successfully carried out and has shown good performance.En las instalaciones de tipo Fuentes de luz de sincrotrón de haz de electrones de alta energía y baja emitancia se aplican diferentes técnicas de mejora de la calidad de la luz de sincrotrón. Con este objetivo, el ALBA, la fuente española de luz de sincrotrón de la tercera generación, está desarrollando un sistema de radiofrecuencia (RF) de la 3ª Harmónica como un sistema adicional al sistema de RF principal del anillo de almacenamiento. Este sistema consistirá de cuatro cavidades activas de conductividad normal de frecuencia 1,5 GHz que suministrarán un voltaje acelerador de 1.1 MV necesario para el haz de electrones y que serán alimentadas por cuatro transmisores de potencia de 20 kW. Esta potencia será generada en modo de onda continua a frecuencia 1.5 GHz por amplificadores de potencia de estado sólido (APES) de estructura modular. A partir de unos estudios preliminares se ha decidido que la arquitectura de cada transmisor de potencia de 20 kW es de tipo diagrama de árbol que consiste de APES primarios de potencia 1 kW conectados en paralelo formando una matriz de combinación. El tema de la presente tesis es el diseño, la construcción y la caracterización de un prototipo del módulo de APES de potencia 1 kW formado por cuatro amplificadores primarios de 250 W de potencia. También, todos subsistemas, concretamente los circuitos de adaptación de entrada y de salida del módulo primario de 250 kW, así como un divisor de cuatro salidas, un combinador de cuatro entradas y un acoplador direccional con una nova solución de compensación de directividad para una monitorización no invasiva han sido diseñados y sus prototipos han sido testeados. La evaluación final de funcionamiento del APES de 1 kW de potencia ha sido realizada con éxito y ha demostrado su buen rendimiento

Circuits for Analog Signal Processing Employing Unconventional Active Elements

Disertační práce se zabývá zaváděním nových struktur moderních aktivních prvků pracujících v napěťovém, proudovém a smíšeném režimu. Funkčnost a chování těchto prvků byly ověřeny prostřednictvím SPICE simulací. V této práci je zahrnuta řada simulací, které dokazují přesnost a dobré vlastnosti těchto prvků, přičemž velký důraz byl kladen na to, aby tyto prvky byly schopny pracovat při nízkém napájecím napětí, jelikož poptávka po přenosných elektronických zařízeních a implantabilních zdravotnických přístrojích stále roste. Tyto přístroje jsou napájeny bateriemi a k tomu, aby byla prodloužena jejich životnost, trend navrhování analogových obvodů směřuje k stále většímu snižování spotřeby a napájecího napětí. Hlavním přínosem této práce je návrh nových CMOS struktur: CCII (Current Conveyor Second Generation) na základě BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na základě FG, transkonduktor na základě nové techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na základě GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na základě GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na základě BD. Dále je uvedeno několik zajímavých aplikací užívajících výše jmenované prvky. Získané výsledky simulací odpovídají teoretickým předpokladům.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.

Amplifier Architectures for Wireless Communication Systems

Ever-increasing demand in modern wireless communication systems leads researchers to focus on design challenges on one of the main components of RF transmitters and receivers, namely amplifiers. On the transmitter side, enhanced efficiency and broader bandwidth over single and multiple bands on power amplifiers will help to have superior performance in communication systems. On the other hand, for the receiver side, having low noise and high gain will be necessary to ensure good quality transmission over such systems. In light of these considerations, a unique approach in design methodologies are studied with low noise amplifiers (LNAs) for RF receivers and the Doherty technique is analyzed for efficiency enhancement for power amplifiers (PA) on the transmitters. This work can be outlined in two parts. In the first part, Low Noise RF amplifier designs with Bipolar Junction Transistor (BJT) are studied to achieve better performing LNAs for receivers. The aim is to obtain a low noise figure while optimizing the bandwidth and achieving a maximum available gain. There are two designs that are operating at different center frequencies and utilizing different transistors. The first design is a wideband low-noise amplifier operating at 2 GHz with a high power BJT. The proposed design uses only distributed elements to realize the input and output matching networks. Additionally, a passive DC bias network is used instead of an active DC bias network to avoid possible complications due to the lumped elements parasitic effects. The matching networks are designed based on the reflection coefficients that are derived based on the transistor’s available regions. The second design is a low voltage standing wave ratio (VSWR) amplifier with a low noise figure operating at 3 GHz. This design is following the same method as in the first design. Both these amplifiers are designed to operate in broadband applications and can be good candidates for base stations. The second part of this work focuses on the transmitter side of communication systems. For this part, Doherty Power Amplifier (DPA) is analyzed as an efficiency enhancement technique for PAs. A modified architecture is proposed to have wider bandwidth and higher efficiency. In the proposed design, the quarter-wave impedance inverter was eliminated. The input and the output of the main and peak amplifiers are matched to the load directly. Additionally, the input and output matching networks are realized only using distributed elements. The selected transistor for this design is a 10 W Gallium Nitride (GaN). The fabricated amplifier operates at the center frequency of 2 GHz and provides 40% fractional bandwidth, 54% of maximum power-added efficiency, and 12.5 dB or better small-signal gain. The design is showing promising results to be a good candidate for better-performing transmitters over the L- and S- band

Advanced CMOS Integrated Circuit Design and Application

The recent development of various application systems and platforms, such as 5G, B5G, 6G, and IoT, is based on the advancement of CMOS integrated circuit (IC) technology that enables them to implement high-performance chipsets. In addition to development in the traditional fields of analog and digital integrated circuits, the development of CMOS IC design and application in high-power and high-frequency operations, which was previously thought to be possible only with compound semiconductor technology, is a core technology that drives rapid industrial development. This book aims to highlight advances in all aspects of CMOS integrated circuit design and applications without discriminating between different operating frequencies, output powers, and the analog/digital domains. Specific topics in the book include: Next-generation CMOS circuit design and application; CMOS RF/microwave/millimeter-wave/terahertz-wave integrated circuits and systems; CMOS integrated circuits specially used for wireless or wired systems and applications such as converters, sensors, interfaces, frequency synthesizers/generators/rectifiers, and so on; Algorithm and signal-processing methods to improve the performance of CMOS circuits and systems

Testing a CMOS operational amplifier circuit using a combination of oscillation and IDDQ test methods

This work presents a case study, which attempts to improve the fault diagnosis and testability of the oscillation testing methodology applied to a typical two-stage CMOS operational amplifier. The proposed test method takes the advantage of good fault coverage through the use of a simple oscillation based test technique, which needs no test signal generation and combines it with quiescent supply current (IDDQ) testing to provide a fault confirmation. A built in current sensor (BICS), which introduces insignificant performance degradation of the circuit-under-test (CUT), has been utilized to monitor the power supply quiescent current changes in the CUT. The testability has also been enhanced in the testing procedure using a simple fault-injection technique. The approach is attractive for its simplicity, robustness and capability of built-in-self test (BIST) implementation. It can also be generalized to the oscillation based test structures of other CMOS analog and mixed-signal integrated circuits. The practical results and simulations confirm the functionality of the proposed test method

Low cost ground receiving systems for television signals from high powered communications satellites, volume 1

The fabrication and evaluation of 10 engineering prototype ground signal processing systems of three converter types are reported for use with satellite television. Target cost converters and cost sensitivity analysis are discussed along with the converter configurations

Architectural Alternatives to Implement High-Performance Delta-Sigma Modulators

RÉSUMÉ Le besoin d’appareils portatifs, de téléphones intelligents et de systèmes microélectroniques implantables médicaux s’accroît remarquablement. Cependant, l’optimisation de l’alimentation de tous ces appareils électroniques portables est l’un des principaux défis en raison du manque de piles à grande capacité utilisées pour les alimenter. C’est un fait bien établi que le convertisseur analogique-numérique (CAN) est l’un des blocs les plus critiques de ces appareils et qu’il doit convertir efficacement les signaux analogiques au monde numérique pour effectuer un post-traitement tel que l’extraction de caractéristiques. Parmi les différents types de CAN, les modulateurs Delta Sigma (��M) ont été utilisés dans ces appareils en raison des fonctionnalités alléchantes qu’ils offrent. En raison du suréchantillonnage et pour éloigner le bruit de la bande d’intérêt, un CAN haute résolution peut être obtenu avec les architectures ��. Il offre également un compromis entre la fréquence d’échantillonnage et la résolution, tout en offrant une architecture programmable pour réaliser un CAN flexible. Ces CAN peuvent être implémentés avec des blocs analogiques de faible précision. De plus, ils peuvent être efficacement optimisés au niveau de l’architecture et circuits correspondants. Cette dernière caractéristique a été une motivation pour proposer différentes architectures au fil des ans. Cette thèse contribue à ce sujet en explorant de nouvelles architectures pour optimiser la structure ��M en termes de résolution, de consommation d’énergie et de surface de silicium. Des soucis particuliers doivent également être pris en compte pour faciliter la mise en œuvre du ��M. D’autre part, les nouveaux procédés CMOS de conception et fabrication apportent des améliorations remarquables en termes de vitesse, de taille et de consommation d’énergie lors de la mise en œuvre de circuits numériques. Une telle mise à l’échelle agressive des procédés, rend la conception de blocs analogiques tel que un amplificateur de transconductance opérationnel (OTA), difficile. Par conséquent, des soins spéciaux sont également pris en compte dans cette thèse pour surmonter les problèmes énumérés. Ayant mentionné ci-dessus que cette thèse est principalement composée de deux parties principales. La première concerne les nouvelles architectures implémentées en mode de tension et la seconde partie contient une nouvelle architecture réalisée en mode hybride tension et temps.----------ABSTRACT The need for hand-held devices, smart-phones and medical implantable microelectronic sys-tems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of long life-time batteries utilized to power them up. It is a well-established fact that analog-to-digital converter (ADC) is one of the most critical building blocks of such devices and it needs to efficiently convert analog signals to the digital world to perform post processing such as channelizing, feature extraction, etc. Among various type of ADCs, Delta Sigma Modulators (��Ms) have been widely used in those devices due to the tempting features they offer. In fact, due to oversampling and noise-shaping technique a high-resolution ADC can be achieved with �� architectures. It also offers a compromise between sampling frequency and resolution while providing a highly-programmable approach to realize an ADC. Moreover, such ADCs can be implemented with low-precision analog blocks. Last but not the least, they are capable of being effectively power optimized at both architectural and circuit levels. The latter has been a motivation to proposed different architectures over the years.This thesis contributes to this topic by exploring new architectures to effectively optimize the ��M structure in terms of resolution, power consumption and chip area. Special cares must also be taken into account to ease the implementation of the ��M. On the other hand, advanced node CMOS processes bring remarkable improvements in terms of speed, size and power consumption while implementing digital circuits. Such an aggressive process scaling, however, make the design of analog blocks, e.g. operational transconductance amplifiers (OTAs), cumbersome. Therefore, special cares are also taken into account in this thesis to overcome the mentioned issues. Having had above mentioned discussion, this thesis is mainly split in two main categories. First category addresses new architectures implemented in a pure voltage domain and the second category contains new architecture realized in a hybrid voltage and time domain. In doing so, the thesis first focuses on a switched-capacitor implementation of a ��M while presenting an architectural solution to overcome the limitations of the previous approaches. This limitations include a power hungry adder in a conventional feed-forward topology as well as power hungry OTAs