Low-voltage Tracking RC Compensated OTA and a Rail-to-Rail Input and Output Operational Amplifier

The operational transconductance amplifier (OTA) is a fundamental building block in analog and mixed-signal systems. This research describes a process-, voltage-, and temperature- (PVT) insensitive low-voltage tracking RC compensation scheme considered for two-stage CMOS OTAs, which cancels the pole due to the load capacitance using a Miller zero generated by the frequency compensation network. A low-voltage current source with no back-gate effect (a “k’ generator” or a peaking current source) is used to generate the bias currents for the OTA. This architecture implemented in a TSMC 180nm CMOS process, achieves a 2X power reduction compared to a widely-used active-RC compensation scheme. Also, a rail-to-rail input and output operational amplifier is designed in a 180nm process with a complementary input pair and a class-AB output stage

A low-offset low-voltage CMOS Op Amp with rail-to-rail input and output ranges

A low voltage CMOS op amp is presented. The circuit uses complementary input pairs to achieve a rail-to-rail common mode input voltage range. Special attention has been given to the reduction of the op amp's systematic offset voltage. Gain boost amplifiers are connected in a special way to provide not only an increase of the low-frequency open-loop gain but also a significant reduction of the systematic offset voltag

A CMOS class-AB transconductance amplifier for switched-capacitor applications

A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high slew-rate (5 V/μs) can be obtained by applying a large bias current to the core OTA. Due to the class-AB operation of the output stage, a high output impedance can be obtained by applying a small bias current to the output stage, resulting in a high DC-gain (61.6 dB). When the performance of this class-AB OTA is compared with that of basic single-stage OTAs it is found that the output impedance of the class-AB OTA is increased without limiting the bandwidth or slew-rat

Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switchedcapacitor applications

ABSTRACT This paper presents a new fully differential operational transconductance amplifier (OTA) for low-voltage and fastsettling switched-capacitor circuits in digital CMOS technology. The proposed two-stage OTA is a hybrid class A/AB that combines a folded cascode as the first stage with active current mirrors as the second stage. It employs a hybrid cascode compensation scheme, merged Ahuja and improved Ahuja style compensations, for fast settling

A Survey of Non-conventional Techniques for Low-voltage Low-power Analog Circuit Design

Designing integrated circuits able to work under low-voltage (LV) low-power (LP) condition is currently undergoing a very considerable boom. Reducing voltage supply and power consumption of integrated circuits is crucial factor since in general it ensures the device reliability, prevents overheating of the circuits and in particular prolongs the operation period for battery powered devices. Recently, non-conventional techniques i.e. bulk-driven (BD), floating-gate (FG) and quasi-floating-gate (QFG) techniques have been proposed as powerful ways to reduce the design complexity and push the voltage supply towards threshold voltage of the MOS transistors (MOST). Therefore, this paper presents the operation principle, the advantages and disadvantages of each of these techniques, enabling circuit designers to choose the proper design technique based on application requirements. As an example of application three operational transconductance amplifiers (OTA) base on these non-conventional techniques are presented, the voltage supply is only ±0.4 V and the power consumption is 23.5 µW. PSpice simulation results using the 0.18 µm CMOS technology from TSMC are included to verify the design functionality and correspondence with theory

Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit

Design of a Low Voltage Class AB Variable Gain Amplifier (VGA)

A variable gain amplifier (VGA) is one of the most significant component in many applications such as analog to digital converter (ADC). In communication receiver, VGA is typically employed in a feedback loop to realize an automatic gain control (AGC), to provide constant signal power to baseband analog-to-digital converter (ADC) for unpredictable received signal strengths. Gain range, power consumption and bandwidth of ADC are strongly influenced by the performance of operational amplifier. VGA is the key element for amplifying process in ADC. However, current class AB VGA is experiencing the limit of bandwidth, which is not suitable for high speed automatic gain control AGC. In order to overcome these limitations a high linearity and wide bandwidth of VGA is indispensable. The aim of this research is to get higher gain and larger bandwidth for VGA. In this research, a low cost, low power voltage and wide bandwidth class AB VGA is designed to mitigate this constraint. Superiority of the proposed VGA has been confirmed by circuit simulation using CEDEC 0.18-μm CMOS process with the help of tools from Mentor Graphics in designing a 100-MHz VGA under 1V supply voltage draining total static power consumption less than 125uW. The results show that the circuit is able to work with high linearity and wide bandwidth by varying Rf and Rs. Therefore, the frequency response (Gain) and the wide bandwidth of this class AB VGA is better than previously reported class AB VGA. Consequently, this modified class AB VGA is appropriate for high speed applications

Design of A Low Power Low Voltage CMOS Opamp

In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp is fairly small (0.0084 mm 2) and slew rate is more than other low power low voltage opamps reported at 0.8 um technology [1,2]. Vittoz at al [3] reported that slew rate can be improved by adaptive biasing technique and power dissipation can be reduced by operating the device in weak inversion. Though lower power dissipation is achieved the area required by the circuit is very large and speed is too small. So, operating the device in moderate inversion is a good solution. Also operating the device in subthreshold region not only allows lower power dissipation but also a lower voltage operation is achieved.Comment: 8 Pages, VLSICS Journa

Assessment of ecosystem integrity of lowland dipterocarp forest ecosystem using remote sensing

Ecosystem Integrity Index (EII) is a concept to determine the quality or the health of an ecosystem. The EII development can assist forest managers and decision makers in the conservation effort and forest management in Malaysia through the development of a simple and easy-to-adopt index. The aim of this study is to assess and evaluate the EII through the development of forest structure empirical models from remotely sensed data for lowland dipterocarp forest in Malaysia. The objectives of this study are: (i) to assess the structure and composition of lowland dipterocarp forest in Malaysia, (ii) to develop empirical model for estimating stand structure from remotely sensed data, and (iii) to derive the ecosystem integrity index for lowland dipterocarp forest. Tree Basal Area (BA), aboveground biomass (AGB) and volume plot from plot data were used as dependent variables, while remote sensing data from Landsat, Pleiades and LiDAR were used as independent variables for model development. Tree plot census was carried out from 17 to 19 May 2016, while remote sensing data acquisition dates for Landsat, Pleiades and LiDAR were 13 March 2016, 24 January 2015 and April 2015 respectively. Forest Structure Modeling was carried out by means of a correlation analysis with the calibration of dependent and independent data to select the most significant and accurate remote sensing variables to derive empiric equation (model), fitting stage to select the best model with the highest coefficient of determination (R2) and the lowest root mean square error ( RMSE) validation of the final selected. The Ecosystem Integrity Index was developed by the average percentage of the predicted BA, AGB and model volume. The EII was categorised at five integrity levels as high (81–100%), medium high (61–80%), moderate (41–60%), medium low (21–40%) and low (0–20%). A total of 1035 trees with diameter at breast height (DBH) of 5.0 cm and above were recorded in 69.115 ha sampling areas. The total trees recorded represented 150 species from 87 genera and 34 families. Shorea macroptera (Dipterocarpaceae), S. leprosula (Dipterocarpaceae) and S. parviflora (Dipterocarpaceae) are three dominant species, with Species Important Value Index (SIVi) of 6.49%, 6.23% and 5.51%, respectively. Dipterocarpaceae is the most dominant with Family Important Value Index (FIVi) of 33.54%. The developed final model is robust and consistent with high R2 with range of 0.84 to 0.87. The final models constructed for AGB, BA and volume value of R2 are 0.85, 0.84 and 0.87 respectively. The RMSE of AGB, BA and volume model are 53.1 Mg/ha, 3.54 m2/ha and 46.4 m3/ha, respectively. The overall stand AGB, BA and volume for Sungai Menyala Forest Reserve is 282.29 Mg/ha, 17.68 m2/ha and 239.51 m3/ha. An Ecosystem Integrity Index (EII) assessment has been successfully demonstrated by this study with production of practical, multi-scaled, flexible, adjustable and policy-relevant index. The overall EII of Sungai Menyala Forest Reserve is in Category 3, which shows that the area is within the medium value