66 research outputs found
The PreAmplifier ShAper for the ALICE TPC-Detector
In this paper the PreAmplifier ShAper (PASA) for the Time Projection Chamber
(TPC) of the ALICE experiment at LHC is presented. The ALICE TPC PASA is an
ASIC that integrates 16 identical channels, each consisting of Charge Sensitive
Amplifiers (CSA) followed by a Pole-Zero network, self-adaptive bias network,
two second-order bridged-T filters, two non-inverting level shifters and a
start-up circuit. The circuit is optimized for a detector capacitance of 18-25
pF. For an input capacitance of 25 pF, the PASA features a conversion gain of
12.74 mV/fC, a peaking time of 160 ns, a FWHM of 190 ns, a power consumption of
11.65 mW/ch and an equivalent noise charge of 244e + 17e/pF. The circuit
recovers smoothly to the baseline in about 600 ns. An integral non-linearity of
0.19% with an output swing of about 2.1 V is also achieved. The total area of
the chip is 18 mm and is implemented in AMS's C35B3C1 0.35 micron CMOS
technology. Detailed characterization test were performed on about 48000 PASA
circuits before mounting them on the ALICE TPC front-end cards. After more than
two years of operation of the ALICE TPC with p-p and Pb-Pb collisions, the PASA
has demonstrated to fulfill all requirements
Performance enhancement in the desing of amplifier and amplifier-less circuits in modern CMOS technologies.
In the context of nowadays CMOS technology downscaling and the increasing demand of high performance electronics by industry and consumers, analog design has become a major challenge.
On the one hand, beyond others, amplifiers have traditionally been a key cell for many analog systems whose overall performance strongly depends on those of the amplifier. Consequently, still today, achieving high performance amplifiers is essential. On the other hand, due to the increasing difficulty in achieving high performance amplifiers in downscaled modern technologies, a different research line that replaces the amplifier by other more easily achievable cells appears: the so called amplifier-less techniques.
This thesis explores and contributes to both philosophies. Specifically, a lowvoltage differential input pair is proposed, with which three multistage amplifiers in the state of art are designed, analysed and tested. Moreover, a structure for the implementation of differential switched capacitor circuits, specially suitable for comparator-based circuits, that features lower distortion and less noise than the classical differential structures is proposed, an, as a proof of concept, implemented in a ΔΣ modulator
HIGH PERFORMANCE CMOS WIDE-BAND RF FRONT-END WITH SUBTHRESHOLD OUT OF BAND SENSING
In future, the radar/satellite wireless communication devices must support multiple standards
and should be designed in the form of system-on-chip (SoC) so that a significant reduction
happen on cost, area, pins, and power etc. However, in such device, the design of a fully
on-chip CMOS wideband receiver front-end that can process several radar/satellite signal simultaneously
becomes a multifold complex problem. Further, the inherent high-power out-of-band
(OB) blockers in radio spectrum will make the receiver more non-linear, even sometimes saturate
the receiver. Therefore, the proper blocker rejection techniques need to be incorporated.
The primary focus of this research work is the development of a CMOS high-performance low
noise wideband receiver architecture with a subthreshold out of band sensing receiver. Further,
the various reconfigurable mixer architectures are proposed for performance adaptability of a
wideband receiver for incoming standards. Firstly, a high-performance low- noise bandwidthenhanced
fully differential receiver is proposed. The receiver composed of a composite transistor
pair noise canceled low noise amplifier (LNA), multi-gate-transistor (MGTR) trans-conductor
amplifier, and passive switching quad followed by Tow Thomas bi-quad second order filter based
tarns-impedance amplifier. An inductive degenerative technique with low-VT CMOS architecture
in LNA helps to improve the bandwidth and noise figure of the receiver. The full receiver
system is designed in UMC 65nm CMOS technology and measured. The packaged LNA provides
a power gain 12dB (including buffer) with a 3dB bandwidth of 0.3G – 3G, noise figure of 1.8 dB
having a power consumption of 18.75mW with an active area of 1.2mm*1mm. The measured
receiver shows 37dB gain at 5MHz IF frequency with 1.85dB noise figure and IIP3 of +6dBm,
occupies 2mm*1.2mm area with 44.5mW of power consumption. Secondly, a 3GHz-5GHz auxiliary
subthreshold receiver is proposed to estimate the out of blocker power. As a redundant
block in the system, the cost and power minimization of the auxiliary receiver are achieved
via subthreshold circuit design techniques and implementing the design in higher technology
node (180nm CMOS). The packaged auxiliary receiver gives a voltage gain of 20dB gain, the
noise figure of 8.9dB noise figure, IIP3 of -10dBm and 2G-5GHz bandwidth with 3.02mW power
consumption. As per the knowledge, the measured results of proposed main-high-performancereceiver
and auxiliary-subthreshold-receiver are best in state of art design. Finally, the various
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reconfigurable mixers architectures are proposed to reconfigure the main-receiver performance
according to the requirement of the selected communication standard. The down conversion mixers
configurability are in the form of active/passive and Input (RF) and output (IF) bandwidth
reconfigurability. All designs are simulated in 65nm CMOS technology. To validate the concept,
the active/ passive reconfigurable mixer configuration is fabricated and measured. Measured
result shows a conversion gain of 29.2 dB and 25.5 dB, noise figure of 7.7 dB and 10.2 dB, IIP3 of
-11.9 dBm and 6.5 dBm in active and passive mode respectively. It consumes a power 9.24mW
and 9.36mW in passive and active case with a bandwidth of 1 to 5.5 GHz and 0.5 to 5.1 GHz
for active/passive case respectively
A capacitor-less low drop-out voltage regulator with fast transient response
Power management has had an ever increasing role in the present electronic industry.
Battery powered and handheld applications require power management techniques to extend the
life of the battery and consequently the operation life of the device. Most systems incorporate
several voltage regulators which supply various subsystems and provide isolation among such
subsystems. Low dropout (LDO) voltage regulators are generally used to supply low voltage,
low noise analog circuitry. Each LDO regulator demands a large external capacitor, in the range
of a few microfarads, to perform. These external capacitors occupy valuable board space,
increase the IC pin count, and prohibit system-on-chip (SoC) solutions.
The presented research provides a solution to the present bulky external capacitor LDO
voltage regulators with a capacitor-less LDO architecture. The large external capacitor was
completely removed and replaced with a reasonable 100pF internal output capacitor, allowing
for greater power system integration for SoC applications. A new compensation scheme is
presented that provides both a fast transient response and full range ac stability from a 0mA to
50mA load current. A 50mA, 2.8V, capacitor-less LDO voltage regulator was fabricated in a
TSMC 0.35um CMOS technology, consuming only 65uA of ground current with a dropout
voltage of 200mV.
Experimental results show that the proposed capacitor-less LDO voltage regulator exceeds
the current published works in both transient response and ac stability. The architecture is also
less sensitive to process variation and loading conditions. Thus, the presented capacitor-less
LDO voltage regulator is suitable for SoC solutions
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