A 4.5-5.8 GHz Differential LC VCO using 0.35 m SiGe BiCMOS Technology

In this paper, design and realization of a 4.5-5.8 GHz, Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is implemented with 0.35´m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). A linear, 1300 MHz tuning range is measured with accumulation-mode varactors. Fundamental frequency output power changes between -1.6 dBm and 0.9 dBm, depending on the tuning voltage. The circuit draws 17 mA from 3.3 V supply, including buffer circuits leading to a total power dissipation of 56 mW. Post-layout phase noise is simulated -110.7 dBc/Hz at 1MHz offset from 5.8 GHz carrier frequency and -113.4 dBc/Hz from 4.5 GHz carrier frequency. Phase noise measurements will be updated in the final manuscript. The circuit occupies an area of 0.6 mm2 on Si substrate including RF and DC pads

Design of a 4.2-5.4 GHz Differential LC VCO using 0.35 m SiGe BiCMOS Technology

In this paper, a 4.2-5.4 GHz, Gm LC voltage controlled oscillator (VCO) for IEEE 802.11a standard is presented. The circuit is designed with AMS 0.35´m SiGe BiCMOS process that includes high-speed SiGe Heterojunction Bipolar Transistors (HBTs). Phase noise is -110.7 dBc/Hz at 1MHz offset from 5.4 GHz carrier frequency and -113.5 dBc/Hz from 4.2 GHz carrier frequency. A linear, 1200 MHz tuning range is obtained utilizing accumulation-mode varactors. Phase noise is relatively low due to taking the advantage of differential tuning concept. Output power of the fundamental frequency changes between 4.8 dBm and 5.5 dBm depending on the tuning voltage. The circuit draws 2 mA without buffers and 14.5 mA from 2.5 V supply including buffer circuits leading to a total power dissipation of 36.25 mW. The circuit occupies an area of 0.6 mm2 on Si substrate including RF and DC pads

The Multiple Gate Mos-Jfet

A new multiple-gate transistor, the SOI MOS-JFET, is presented. This device combines the MOS field effect and junction field effect within one transistor body. Measured I-V characteristics are provided to illustrate typical modes of operation and the functionality associated with each gate. Two-dimensional simulations of the device?s cross-section will be presented to illustrate various conduction modes under different bias conditions. Test results indicate the MOS-JFET is well suited for both high-voltage and low-voltage circuit demands for systems-on-a-chip applications on SOI technology. Analog building-block circuits based the MOS-JFET are also presented

5 GHz Optical Front End in 0.35um CMOS

With the advantages of low cost, low power consumption, high reliability and potential for large scale integration, CMOS monolithically integrated active pixel chips have significant application in optical sensing systems. The optical front end presented in this thesis will have application in Optical Scanning Acoustic Microscope System (O-SAM), which involves a totally non-contact method of acquiring images of the interaction between surface acoustic waves (SAWs) and a solid material to be characterized. In this work, an ultra fast optical front-end using improved regulated cascade scheme is developed based on AMS 0.35mm CMOS technology. The receiver consists of an integrated photodiode, a transimpedance amplifier, a mixer, an IF amplifier and an output buffer. By treating the n-well in standard CMOS technology as a screening terminal to block the slow photo-generated bulk carriers and interdigitizing shallow p+ junctions as the active region, the integrated photodiode operates up to 4.9 GHz with no process modification. Its responsivity was measured to be 0.016 A/W. With multi-inductive-series peaking technique, the improved ReGulated-Cascade (RGC) transimpedance amplifier achieves an experimentally measured -3dB bandwidth of more than 6 GHz and a transimpedance gain of 51 dBW, which is the fastest reported TIA in CMOS 0.35mm technology. The 5 GHz Gilbert cell mixer produces a conversion gain of 11 dB, which greatly minimized the noise contribution from the IF stage. The noise figure and input IIP3 of the mixer were measured to be 15.7 dB and 1.5 dBm, respectively. The IF amplifier and output buffer pick up and further amplify the signal for post processing. The optical front end demonstrates a typical equivalent input noise current of 35 pA=pHz at 5 GHz, and a total transimpedance gain of 83 dB ohm whileconsuming a total current of 40 mA from 3.3 V power supply. The -3 dB bandwidth for the optical front end was measured to be 4.9 GHz. All the prototype chips, including the optical front end, and the individual circuits including the photodiode, TIA, mixer were probe-tested and all the measurements were taken with Anritsu VNA 37397D and Anritsu spectrum analyser MS2721A

Solid-State Imaging in Standard CMOS Processes

The main aim of this work is to investigate the real CMOS imaging possibilities of standard (not CMOS imaging enhanced) 0.5µm and 0.35µm CMOS processes available for in-house fabrication at the Fraunhofer IMS by performing an extensive study of standard available photodetector structures, mainly based on reverse biased p-n junctions and/or metal-oxide-semiconductor capacitors (MOS-C). Moreover, novel concepts of photodetector pixel structures and readout circuits are proposed, modelled, simulated, fabricated, and characterised, that should achieve an improvement in performance as well as new application developments in the area of CMOS imaging systems. The latter, undergoing as a small amount of changes (extra masks, thermal steps, ion implantations, etc.) as possible within the standard CMOS processes mentioned. In this sense, in Chapter 1 a brief review of the fundamentals of silicon oriented photodetection and electronic devices physics is given, some of the basic postulates of which are directly applied to the case of the 0.5µm standard CMOS process available at the Fraunhofer IMS, whose photodetection possibilities are investigated in detail in Chapter 2. Chapter 3 deals with different pixel configuration possibilities to be fabricated in the 0.5µm process. As a potential solution to overcome some of the problems encountered in Chapter 3, in Chapter 4, the possibilities of using separated photoactive and readout regions in a mixed silicon-on-insulator (SOI) based high-voltage CMOS process developed for automotive industry applications are discussed. Moreover, the same 30V thin-film SOI CMOS process is proposed for direct (not using a scintillator material) X-ray scientific CMOS imaging applications, as it is explained in Chapter 5. In Chapter 6, the photodetection possibilities of the recently developed 0.35µm standard CMOS process available at the Fraunhofer IMS are investigated, as well as different pixel configurations possible to be fabricated in this process. Finally, a discussion is carried out regarding the results obtained throughout the enlisted chapters, and new lines of investigation are attempted to be opened based on some of the results obtained in the present investigation.Das Hauptthema dieser Dissertation ist die Untersuchung vorhandener und neuer Photodetektoren für die CMOS-Bildsensorik, insbesondere in Bezug auf die technologischen und optoelektronischen Eigenschaften sowie das Rauschen. Durch die gründliche Charakterisierung vorhandener und neuer Photodetektoren und deren Ausleseschaltungen, hergestellt in den 0,5µm, 0,35µm und 1,0µm SOI Standard CMOS Prozessen, wurde das vorhandene Wissen vertieft und erweitert. Auf dieser Basis wurden neue Bauelemente für die 2D- und 3D-Bildsensorik entworfen und bereits vorhandene optimiert. Zum besseren Verständnis der Bauelementenstruktur, und um die Anzahl von Fertigungsdurchläufen für neuartige Photodetektorbauelementen zu reduzieren, wurde die Prozess- und Bauelemente-Simulationsumgebung (ISE-Synopsys) TCAD genutzt. Ziel dabei war es, neu entwickelte Bauelemente vor einer Fertigung bezüglich ihrer Schlüsselspezifikationen zu optimieren und qualitativ bewerten zu können. Ferner wurden passende Ausleseschaltungen für die Photodetektorbauelemente entwickelt. Somit konnte ein System aus Photodetektor und Ausleseschaltung optimal auf eine Anwendung abgestimmt werden. Um die Entwurfsicherheit von CMOS Photodetektoren und Ausleseschaltungen zu erhöhen, wurde zur Modellierung von Photodetektorbauelementen mit den Softwarepaketen MAPLE und Fortran eine Entwicklungsumgebung aufgebaut. Auf Basis der so gewonnenen Spezifikationen der Photodetektorstrukturen konnten die gesamten Pixel mit der Schaltungsentwicklungsumgebung CADENCE simuliert werden. Anschließend wurden diese Detektoren und Ausleseschaltungen in den 0,5µm und 0,35µm Standard CMOS Prozessen sowie in dem 1,0µm SOI CMOS Prozess hergestellt und getestet. Um das Signal-Rausch-Verhältnis (SNR) zu verbessern, wurden verschiedenen Pixelkonfigurationen mit voneinander getrennten Photoaktiv- und Auslesegebieten untersucht, wie z.B. in den „Photogate“- oder „Buried-Photodiode“ Aktiv Pixelsensoren. Es wurde allerdings gezeigt, dass die Ladungskopplung, die für die Auslese bei solchen Pixel notwendig ist, bei keiner Kombination der Photodetektoren und der Auslesegebiete im 0,5µm Standard CMOS Prozess funktioniert. Anschließend wurden Untersuchungen von unterschiedlichen Pixelalternativen mit innovativen Ausleseprinzipien durchgeführt. Eines der neu entwickelten Ausleseprinzipien wurde am „Charge-Injection-Photogate-Pixel“ getestet. Durch dieses Ausleseprinzip entsteht eine große interne Verstärkung. Danach wurde dieses Ausleseprinzip auf einer SOI-Struktur angewendet. Dabei werden alle Vorteile eines Hochspannungs- und Hochtemperaturprozesses zusammen mit den Möglichkeiten genutzt, die ein Standard CMOS Prozess zur Integration der Ausleseelektronik auf dem selben Chip erlaubt. Im Rahmen dieser Dissertation wurde darüber hinaus die Möglichkeit untersucht, die Indium-Zinn-Oxid (ITO) Schichten im 0,5µm Standard CMOS Prozess als Gate-Material einzusetzen. Dies bewirkt einen höheren Quantumwirkungsgrad im sichtbaren Wellenlängenbereich, wenn es bei Photogate-Pixel angewandt wird. Im Nah-Infrarot Wellenlängenbereich jedoch bringt es keine Vorteile gegenüber dem standardmäßig verwendeten Polysilizium. Anschließend wurden verschiedene Pixelstrukturen im 0,35µm Standard CMOS Prozess entworfen und simuliert. Dabei wurde gezeigt, dass zumindest theoretisch das Ladungskopplungsprinzip bei den auf „Photogates“ und auf „Buried-Photodioden“ basierenden Strukturen funktioniert

5 GHz Optical Front End in 0.35um CMOS

With the advantages of low cost, low power consumption, high reliability and potential for large scale integration, CMOS monolithically integrated active pixel chips have significant application in optical sensing systems. The optical front end presented in this thesis will have application in Optical Scanning Acoustic Microscope System (O-SAM), which involves a totally non-contact method of acquiring images of the interaction between surface acoustic waves (SAWs) and a solid material to be characterized. In this work, an ultra fast optical front-end using improved regulated cascade scheme is developed based on AMS 0.35mm CMOS technology. The receiver consists of an integrated photodiode, a transimpedance amplifier, a mixer, an IF amplifier and an output buffer. By treating the n-well in standard CMOS technology as a screening terminal to block the slow photo-generated bulk carriers and interdigitizing shallow p+ junctions as the active region, the integrated photodiode operates up to 4.9 GHz with no process modification. Its responsivity was measured to be 0.016 A/W. With multi-inductive-series peaking technique, the improved ReGulated-Cascade (RGC) transimpedance amplifier achieves an experimentally measured -3dB bandwidth of more than 6 GHz and a transimpedance gain of 51 dBW, which is the fastest reported TIA in CMOS 0.35mm technology. The 5 GHz Gilbert cell mixer produces a conversion gain of 11 dB, which greatly minimized the noise contribution from the IF stage. The noise figure and input IIP3 of the mixer were measured to be 15.7 dB and 1.5 dBm, respectively. The IF amplifier and output buffer pick up and further amplify the signal for post processing. The optical front end demonstrates a typical equivalent input noise current of 35 pA=pHz at 5 GHz, and a total transimpedance gain of 83 dB ohm whileconsuming a total current of 40 mA from 3.3 V power supply. The -3 dB bandwidth for the optical front end was measured to be 4.9 GHz. All the prototype chips, including the optical front end, and the individual circuits including the photodiode, TIA, mixer were probe-tested and all the measurements were taken with Anritsu VNA 37397D and Anritsu spectrum analyser MS2721A

A Low Power 5.8GHz Fully Integrated CMOS LNA for Wireless Applications

A low power 5.8 GHz fully integrated CMOS low noise amplifier (LNA) with on chip spiral inductors for wireless applications is designed based on TSMC 0.18 µm technology in this paper. The cascode structure and power-constrained simultaneous noise and input matching technique are adopted to achieve low noise, low power and high gain characteristics. The proposed LNA exhibit a state of the art performance consuming only 6.4mW from a 1.8V power supply. The simulation results show that it has a noise figure (NF) only 0.972 dB, which is perfectly close to NFmin while maintaining the other performances. The proposed LNA also has an input 1-dB compression point (IP1dB) of-21.22 dBm, a power gain of 17.04 dB, and good input and output reflection coefficients, which indicate that the proposed LNA topology is very suitable for the implementation of narrowband LNAs in 802.11a wireless applications

CMOS analog integrated circuit design techniques for low-powered ubiquitous device

制度:新 ; 文部省報告番号:甲2633号 ; 学位の種類:博士(工学) ; 授与年月日:2008/3/15 ; 早大学位記番号:新479