1,785 research outputs found

    A low-power asynchronous data-path for a FIR filter bank

    Get PDF

    A Scalable Correlator Architecture Based on Modular FPGA Hardware, Reuseable Gateware, and Data Packetization

    Full text link
    A new generation of radio telescopes is achieving unprecedented levels of sensitivity and resolution, as well as increased agility and field-of-view, by employing high-performance digital signal processing hardware to phase and correlate large numbers of antennas. The computational demands of these imaging systems scale in proportion to BMN^2, where B is the signal bandwidth, M is the number of independent beams, and N is the number of antennas. The specifications of many new arrays lead to demands in excess of tens of PetaOps per second. To meet this challenge, we have developed a general purpose correlator architecture using standard 10-Gbit Ethernet switches to pass data between flexible hardware modules containing Field Programmable Gate Array (FPGA) chips. These chips are programmed using open-source signal processing libraries we have developed to be flexible, scalable, and chip-independent. This work reduces the time and cost of implementing a wide range of signal processing systems, with correlators foremost among them,and facilitates upgrading to new generations of processing technology. We present several correlator deployments, including a 16-antenna, 200-MHz bandwidth, 4-bit, full Stokes parameter application deployed on the Precision Array for Probing the Epoch of Reionization.Comment: Accepted to Publications of the Astronomy Society of the Pacific. 31 pages. v2: corrected typo, v3: corrected Fig. 1

    Low power digital signal processing

    Get PDF

    A low-power asynchronous VLSI FIR filter

    Get PDF
    An asynchronous FIR filter, based on a Single Bit-Plane architecture with a data-dependent, dynamic-logic implementation, is presented. Its energy consumption and sample computation delay are shown to correlate approximately linearly with the total number of ones in its coeflcient-set. The proposed architecture has the property that coefficients in a Sign-Magnitude representation can be handled at negligible overhead which, for typical filter coefficient-sets, is shown to offer significant benefits to both energy consumption and throughput. Transistor level simulations show energy consumption to be lower than in previously reported designs

    Microsemi RTG4 Rev C Field Programmable Gate Array Single Event Effects (SEE) Heavy-Ion Test Report

    Get PDF
    The goal of this study was to perform an independent investigation of single event destructive and transient susceptibility of the Microsemi RTG4 device. The devices under test were the Microsemi RTG4 field programmable gate array (FPGA) Rev C. The devices under test will be referenced as the DUT or RTG4 Rev C throughout this document. The DUT was configured to have various test structures that are geared to measure specific potential susceptibilities of the device. DesignDevice susceptibility was determined by monitoring the DUT for Single Event Transient (SET) and Single Event Upset (SEU) induced faults by exposing the DUT to a heavy ion beam. Potential Single Event Latch-up (SEL) was checked throughout heavy-ion testing by monitoring device current

    Adaptive DS-CDMA multiuser detection for time variant frequency selective Rayleigh fading channel

    Get PDF
    The current digital wireless mobile system such as IS-95, which is based on direct sequence Code Division Multiple Access (DS-CDMA) technology, will not be able to meet the growing demands for multimedia service due to low information exchanging rate. Its capacity is also limited by multiple accessed interference (MAI) signals. This work focuses on the development of adaptive algorithms for multiuser detection (MUD) and interference suppression for wideband direct sequence code division multiple access (DS-CDMA) systems over time-variant frequency selective fading channels. In addition, channel acquisition and delay estimation techniques are developed to combat the uncertainty introduced by the wireless propagation channel. This work emphasizes fast and simple techniques that can meet practical needs for high data rate signal detection. Most existing literature is not suitable for the large delay spread in wideband systems due to high computational/ hardware complexity. A de-biasing decorrelator is developed whose computational complexity is greatly reduced without sacrificing performance. An adaptive bootstrap symbolbased signal separator is also proposed for a time-variant channel. These detectors achieve MUD for asynchronous, large delay spread, fading channels without training sequences. To achieve high data rate communication, a finite impulse response (FIR) filter based detector is presented for M-ary QAM modulated signals in a multipath Rayleigh fading channel. It is shown that the proposed detector provides a stable performance for QAM signal detection with unknown fading and phase shift. It is also shown that this detector can be easily extended to the reception of any M-ary quadrature modulated signal. A minimum variance decorrelating (MVD) receiver with adaptive channel estimator is presented in this dissertation. It provides comparable performance to a linear MMSE receiver even in a deep fading environment and can be implemented blindly. Using the MVD receiver as a building-block, an adaptive multistage parallel interference cancellation (PIC) scheme and a successive interference cancellation (SIC) scheme were developed. The total number of stages is kept at a minimum as a result of the accurate estimating of the interfering users at the earliest stages, which reduces the implementation complexity, as well as the processing delay. Jointly with the MVD receiver, a new transmit diversity (TD) scheme, called TD-MVD, is proposed. This scheme improves the performance without increasing the bandwidth. Unlike other TD techniques, this TDMVD scheme has the inherent advantage to overcome asynchronous multipath transmission. It brings flexibility in the design of TD antenna systems without restrict signal coordination among those multiple transmissions, and applicable for both existing and next generation of CDMA systems. A maximum likelihood based delay and channel estimation algorithm with reduced computational complexity is proposed. This algorithm uses a diagonal simplicity technique as well as the asymptotically uncorrelated property of the received signal in the frequency domain. In combination with oversampling, this scheme does not suffer from a singularity problem and the performance quickly approaches the Cramer-Rao lower bound (CRLB) while maintaining a computational complexity that is as low as the order of the signal dimension

    GaAs Implementation of FIR Filter

    Get PDF
    This thesis discusses the findings of the final year project involving Gallium Arsenide implementation of a triangular FIR filter to perform discrete wavelet transforms. The overall characteristics of Gallium Arsenide technology- its construction, behaviour and electrical charactersitics as they apply to VLSI technology - were investigated in this project. In depth understanding of its architecture is required to be able to understand the various design techniques employed. A comparison of Silicon and GaAs performance and other characteristics has also been made to fully justify the choice of this material for system implementation. A lot of research and active interest has gone into the field of image and video compression. Wavelet-based image transformation is one of the very efficient compression techniques used. An analysis of discrete wavelet transformations and the required triangular FIR filter was done to be able to produce a transform algorithm and the related filter architecture. Finally, the filter architecture was implemented as a VLSI design and layout. A variety of functional blocks required for the architecture were designed, tested and analysed. All these blocks were integrated to produce a model of a complete filter cell. The filter implementation was designed to be self-timed - without a system clock. Self-timed systems have considerable advantages over clocked architectures. Various design styles and handshaking mechanisms involved in designing a self-timed system were analysed and designed. There are many avenues still to explore. One of them is the VHDL analysis of filter architecture. Further development on this project would involve integration of higher-level logic and formation of a complete filter array
    • …
    corecore