A Low Power 32 Bit CMOS ROM Using A Novel ATD Circuit

A low power high speed 32 Bit ROM circuit implemented on 0.18µm CMOS process has been presented in this paper. The circuit is build using a parallel ROM core structure and runs on 1.8 V supply voltage. A novel Address Transition Decoder (ATD) circuit is proposed which energizes the ROM components such as Row Decoder, Column Decoder, ROM core etc, for short time intervals when there is a transition in input address bits. The power consumed in ROM with proposed ATD circuit is 0.78 mW, which corresponds to 82.27% reduction in power as compared to ROM without ATD circuit (4.46 mW). At the output almost full signal swing has been achieved without using any sense amplifier. The implemented ROM has a very low latency of 0.56 ns.DOI:http://dx.doi.org/10.11591/ijece.v3i4.316

Emerging embedded nonvolatile memory solution for ultra low power microcontroller systems

13301甲第4810号博士（工学）金沢大学博士論文本文Full 以下に掲載および掲載予定：1.IEEE Journal of Solid-State Circuits 27(4) pp.569-573 1992. IEEE. 共著者：M. Hayashikoshi, H. Hidaka, K. Arimoto, K. Fujishima 2.IEEE Transactions on Multi-Scale Computing Systems IEEE. 共著者：M. Hayashikoshi, H. Noda, H. Kawai, Y. Murai, S. Otani, K. Nii, Y. Matsuda, H. Kond

Autonomous power management of series-cascaded and hybrid microgrids

Microgrids with power electronics interfaced Distributed Generation units are gaining high popularity due to its zero emission characteristics. Control and coordination of these generation units are the most crucial factors that will determine the effective utilisation and flexibility of microgrids. Conventional microgrid structure with droop controlled parallel distributed generation units are being replaced by the series-cascaded structure due to its reduced conversion stages and inherent harmonic sharing capability. This research work first aims to develop a microgrid architecture integrating dispatchable and non-dispatchable distributed generation units in a series-cascaded manner. Existing control strategies for cascaded microgrids focus on dispatchable type generation only. However, adequate power sharing and voltage regulation of a microgrid containing mixed dispatchable and non-dispatchable cascaded generation units demand new control approaches to achieve operational performance and reliability comparable to the conventional parallel-topology microgrid. To ensure maximum utilisation of non-dispatchable units a novel microgrid architecture formed by a dispatchable master unit followed by a set of non-dispatchable slave photovoltaic units in a series-cascaded manner is developed. A fully decentralised control scheme is proposed, which achieves autonomous power balancing and voltage regulation, ensures full utilisation of non-dispatchable generation units, and allows surplus power curtailment under light load conditions. Further, this research work aims to extend the series topological arrangement to form a hybrid microgrid, where low voltage converters are cascaded as a string unit to achieve rated output voltage, and these strings are then paralleled to obtain higher redundancy and power rating. The extension of the arrangement to a hybrid microgrid requires the development of new control strategies, since existing schemes cannot be applied in their original form. As of now hybrid microgrids are controlled using either distributed or centralised schemes to achieve accurate power sharing among the distributed generation units at the cost of complex communication infrastructure. Therefore, a new control scheme is proposed for the hybrid microgrid which aims to achieve accurate power sharing among the paralleled units while maintaining adequate synchronisation among the cascaded converters without any communication link. Fundamental concepts as well as mathematical and simulation models of the existing and proposed control schemes are presented. All the proposed control strategies are validated through extensive simulation results and the series-cascaded microgrid control is validated through matching simulation and experimental results

Energy-efficient analog-to-digital conversion for ultra-wideband radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 207-222).In energy constrained signal processing and communication systems, a focus on the analog or digital circuits in isolation cannot achieve the minimum power consumption. Furthermore, in advanced technologies with significant variation, yield is traditionally achieved only through conservative design and a sacrifice of energy efficiency. In this thesis, these limitations are addressed with both a comprehensive mixed-signal design methodology and new circuits and architectures, as presented in the context of an analog-to-digital converter (ADC) for ultra-wideband (UWB) radio. UWB is an emerging technology capable of high-data-rate wireless communication and precise locationing, and it requires high-speed (>500MS/s), low-resolution ADCs. The successive approximation register (SAR) topology exhibits significantly reduced complexity compared to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network enable the high-speed operation. Finally, only a small amount of redundancy, with negligible power penalty, dramatically improves the yield of the highly parallel ADC in deep sub-micron CMOS.by Brian P. Ginsburg.Ph.D

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

Development of PCI Embedded Card Useful for Microcontroller Trainer

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CIRCUITS AND ARCHITECTURE FOR BIO-INSPIRED AI ACCELERATORS

Technological advances in microelectronics envisioned through Moore’s law have led to powerful processors that can handle complex and computationally intensive tasks. Nonetheless, these advancements through technology scaling have come at an unfavorable cost of significantly larger power consumption, which has posed challenges for data processing centers and computers at scale. Moreover, with the emergence of mobile computing platforms constrained by power and bandwidth for distributed computing, the necessity for more energy-efficient scalable local processing has become more significant. Unconventional Compute-in-Memory architectures such as the analog winner-takes-all associative-memory and the Charge-Injection Device processor have been proposed as alternatives. Unconventional charge-based computation has been employed for neural network accelerators in the past, where impressive energy efficiency per operation has been attained in 1-bit vector-vector multiplications, and in recent work, multi-bit vector-vector multiplications. In the latter, computation was carried out by counting quanta of charge at the thermal noise limit, using packets of about 1000 electrons. These systems are neither analog nor digital in the traditional sense but employ mixed-signal circuits to count the packets of charge and hence we call them Quasi-Digital. By amortizing the energy costs of the mixed-signal encoding/decoding over compute-vectors with many elements, high energy efficiencies can be achieved. In this dissertation, I present a design framework for AI accelerators using scalable compute-in-memory architectures. On the device level, two primitive elements are designed and characterized as target computational technologies: (i) a multilevel non-volatile cell and (ii) a pseudo Dynamic Random-Access Memory (pseudo-DRAM) bit-cell. At the level of circuit description, compute-in-memory crossbars and mixed-signal circuits were designed, allowing seamless connectivity to digital controllers. At the level of data representation, both binary and stochastic-unary coding are used to compute Vector-Vector Multiplications (VMMs) at the array level. Finally, on the architectural level, two AI accelerator for data-center processing and edge computing are discussed. Both designs are scalable multi-core Systems-on-Chip (SoCs), where vector-processor arrays are tiled on a 2-layer Network-on-Chip (NoC), enabling neighbor communication and flexible compute vs. memory trade-off. General purpose Arm/RISCV co-processors provide adequate bootstrapping and system-housekeeping and a high-speed interface fabric facilitates Input/Output to main memory

The 1991 3rd NASA Symposium on VLSI Design

Papers from the symposium are presented from the following sessions: (1) featured presentations 1; (2) very large scale integration (VLSI) circuit design; (3) VLSI architecture 1; (4) featured presentations 2; (5) neural networks; (6) VLSI architectures 2; (7) featured presentations 3; (8) verification 1; (9) analog design; (10) verification 2; (11) design innovations 1; (12) asynchronous design; and (13) design innovations 2