Replacing the automatic gain control loop in a mobile, digital TV broadcast receiver by a software based solution

The power level (the amplitude) of an electro-magnetic signal wave suffers from attenuation the greater the distance between the transmitter and the receiver is. The receiver of that signal therefore has components which try to amplify the signal so that it can be processed optimally by a processor. In a mobile or portable environment the signal power level can vary strongly, because the position of the receiver to the transmitter is not fixed. In order to compensate that movement a control loop exists, which dynamically is adapting the front-end to the right level. This work describes a new, software-based way to handle the signal level control loop (formerly automatic gain control) in a digital TV receiver. Starting with a very basic introduction into digital communications, including the description of the traditional front-end architecture, followed by a detailed description of the new method. Finally some conclusions of this new method are made which are giving an idea about how in the future it might be possible to reach better receiving performances using this mechanism

High-Level Design for Ultra-Fast Software Defined Radio Prototyping on Multi-Processors Heterogeneous Platforms

International audienceThe design of Software Defined Radio (SDR) equipments (terminals, base stations, etc.) is still very challenging. We propose here a design methodology for ultra-fast prototyping on heterogeneous platforms made of GPPs (General Purpose Processors), DSPs (Digital Signal Processors) and FPGAs (Field Programmable Gate Array). Lying on a component-based approach, the methodology mainly aims at automating as much as possible the design from an algorithmic validation to a multi-processing heterogeneous implementation. The proposed methodology is based on the SynDEx CAD design approach, which was originally dedicated to multi-GPPs networks. We show how this was changed so that it is made appropriate with an embedded context of DSP. The implication of FPGAs is then addressed and integrated in the design approach with very little restrictions. Apart from a manual HW/SW partitioning, all other operations may be kept automatic in a heterogeneous processing context. The targeted granularity of the components, which are to be assembled in the design flow, is roughly the same size as that of a FFT, a filter or a Viterbi decoder for instance. The re-use of third party or pre-developed IPs is a basis for this design approach. Thanks to the proposed design methodology it is possible to port "ultra" fast a radio application over several platforms. In addition, the proposed design methodology is not restricted to SDR equipment design, and can be useful for any real-time embedded heterogeneous design in a prototyping context

Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases

[EN] The first generation of Terrestrial Digital Television(DTV) has been in service for over a decade. In 2013, several countries have already completed the transition from Analog to Digital TV Broadcasting, most of which in Europe. In South America, after several studies and trials, Brazil adopted the Japanese standard with some innovations. Japan and Brazil started Digital Terrestrial Television Broadcasting (DTTB) services in December 2003 and December 2007 respectively, using Integrated Services Digital Broadcasting - Terrestrial (ISDB-T), also known as ARIB STD-B31. In June 2005 the Committee for the Information Technology Area (CATI) of Brazilian Ministry of Science and Technology and Innovation MCTI approved the incorporation of the IC-Brazil Program, in the National Program for Microelectronics (PNM) . The main goals of IC-Brazil are the formal qualification of IC designers, support to the creation of semiconductors companies focused on projects of ICs within Brazil, and the attraction of semiconductors companies focused on the design and development of ICs in Brazil. The work presented in this thesis originated from the unique momentum created by the combination of the birth of Digital Television in Brazil and the creation of the IC-Brazil Program by the Brazilian government. Without this combination it would not have been possible to make these kind of projects in Brazil. These projects have been a long and costly journey, albeit scientifically and technologically worthy, towards a Brazilian DTV state-of-the-art low complexity Integrated Circuit, with good economy scale perspectives, due to the fact that at the beginning of this project ISDB-T standard was not adopted by several countries like DVB-T. During the development of the ISDB-T receiver proposed in this thesis, it was realized that due to the continental dimensions of Brazil, the DTTB would not be enough to cover the entire country with open DTV signal, specially for the case of remote localizations far from the high urban density regions. Then, Eldorado Research Institute and Idea! Electronic Systems, foresaw that, in a near future, there would be an open distribution system for high definition DTV over satellite, in Brazil. Based on that, it was decided by Eldorado Research Institute, that would be necessary to create a new ASIC for broadcast satellite reception. At that time DVB-S2 standard was the strongest candidate for that, and this assumption still stands nowadays. Therefore, it was decided to apply to a new round of resources funding from the MCTI - that was granted - in order to start the new project. This thesis discusses in details the Architecture and Algorithms proposed for the implementation of a low complexity Intermediate Frequency(IF) ISDB-T Receiver on Application Specific Integrated Circuit (ASIC) CMOS. The Architecture proposed here is highly based on the COordinate Rotation Digital Computer (CORDIC) Algorithm, that is a simple and efficient algorithm suitable for VLSI implementations. The receiver copes with the impairments inherent to wireless channels transmission and the receiver crystals. The thesis also discusses the Methodology adopted and presents the implementation results. The receiver performance is presented and compared to those obtained by means of simulations. Furthermore, the thesis also presents the Architecture and Algorithms for a DVB-S2 receiver targeting its ASIC implementation. However, unlike the ISDB-T receiver, only preliminary ASIC implementation results are introduced. This was mainly done in order to have an early estimation of die area to prove that the project in ASIC is economically viable, as well as to verify possible bugs in early stage. As in the case of ISDB-T receiver, this receiver is highly based on CORDIC algorithm and it was prototyped in FPGA. The Methodology used for the second receiver is derived from that used for the ISDB-T receiver, with minor additions given the project characteristics.[ES] La primera generación de Televisión Digital Terrestre(DTV) ha estado en servicio por más de una década. En 2013, varios países completaron la transición de transmisión analógica a televisión digital, la mayoría de ellas en Europa. En América del Sur, después de varios estudios y ensayos, Brasil adoptó el estándar japonés con algunas innovaciones. Japón y Brasil comenzaron a prestar el servicio de Difusión de Televisión Digital Terrestre (DTTB) en diciembre de 2003 y diciembre de 2007 respectivamente, utilizando Radiodifusión Digital de Servicios Integrados Terrestres (ISDB-T), también conocida como ARIB STD-B31. En junio de 2005, el Comité del Área de Tecnología de la Información (CATI) del Ministerio de Ciencia, Tecnología e Innovación de Brasil - MCTI aprobó la incorporación del Programa CI-Brasil, en el Programa Nacional de Microelectrónica (PNM). Los principales objetivos de la CI-Brasil son la formación de diseñadores de CIs, apoyar la creación de empresas de semiconductores enfocadas en proyectos de circuitos integrados dentro de Brasil, y la atracción de empresas de semiconductores interesadas en el diseño y desarrollo de circuitos integrados. El trabajo presentado en esta tesis se originó en el impulso único creado por la combinación del nacimiento de la televisión digital en Brasil y la creación del Programa de CI-Brasil por el gobierno brasileño. Sin esta combinación no hubiera sido posible realizar este tipo de proyectos en Brasil. Estos proyectos han sido un trayecto largo y costoso, aunque meritorio desde el punto de vista científico y tecnológico, hacia un Circuito Integrado brasileño de punta y de baja complejidad para DTV, con buenas perspectivas de economía de escala debido al hecho que al inicio de este proyecto, el estándar ISDB-T no fue adoptado por varios países como DVB-T. Durante el desarrollo del receptor ISDB-T propuesto en esta tesis, se observó que debido a las dimensiones continentales de Brasil, la DTTB no sería suficiente para cubrir todo el país con la señal de televisión digital abierta, especialmente para el caso de localizaciones remotas, apartadas de las regiones de alta densidad urbana. En ese momento, el Instituto de Investigación Eldorado e Idea! Sistemas Electrónicos, previeron que en un futuro cercano habría un sistema de distribución abierto para DTV de alta definición por satélite en Brasil. Con base en eso, el Instituto de Investigación Eldorado decidió que sería necesario crear un nuevo ASIC para la recepción de radiodifusión por satélite, basada el estándar DVB-S2. En esta tesis se analiza en detalle la Arquitectura y algoritmos propuestos para la implementación de un receptor ISDB-T de baja complejidad y frecuencia intermedia (IF) en un Circuito Integrado de Aplicación Específica (ASIC) CMOS. La arquitectura aquí propuesta se basa fuertemente en el algoritmo Computadora Digital para Rotación de Coordenadas (CORDIC), el cual es un algoritmo simple, eficiente y adecuado para implementaciones VLSI. El receptor hace frente a las deficiencias inherentes a las transmisiones por canales inalámbricos y los cristales del receptor. La tesis también analiza la metodología adoptada y presenta los resultados de la implementación. Por otro lado, la tesis también presenta la arquitectura y los algoritmos para un receptor DVB-S2 dirigido a la implementación en ASIC. Sin embargo, a diferencia del receptor ISDB-T, se introducen sólo los resultados preliminares de implementación en ASIC. Esto se hizo principalmente con el fin de tener una estimación temprana del área del die para demostrar que el proyecto en ASIC es económicamente viable, así como para verificar posibles errores en etapa temprana. Como en el caso de receptor ISDB-T, este receptor se basa fuertemente en el algoritmo CORDIC y fue un prototipado en FPGA. La metodología utilizada para el segundo receptor se deriva de la utilizada para el re[CA] La primera generació de Televisió Digital Terrestre (TDT) ha estat en servici durant més d'una dècada. En 2013, diversos països ja van completar la transició de la radiodifusió de televisió analògica a la digital, i la majoria van ser a Europa. A Amèrica del Sud, després de diversos estudis i assajos, Brasil va adoptar l'estàndard japonés amb algunes innovacions. Japó i Brasil van començar els servicis de Radiodifusió de Televisió Terrestre Digital (DTTB) al desembre de 2003 i al desembre de 2007, respectivament, utilitzant la Radiodifusió Digital amb Servicis Integrats de (ISDB-T), coneguda com a ARIB STD-B31. Al juny de 2005, el Comité de l'Àrea de Tecnologia de la Informació (CATI) del Ministeri de Ciència i Tecnologia i Innovació del Brasil (MCTI) va aprovar la incorporació del programa CI Brasil al Programa Nacional de Microelectrònica (PNM). Els principals objectius de CI Brasil són la qualificació formal dels dissenyadors de circuits integrats, el suport a la creació d'empreses de semiconductors centrades en projectes de circuits integrats dins del Brasil i l'atracció d'empreses de semiconductors centrades en el disseny i desenvolupament de circuits integrats. El treball presentat en esta tesi es va originar en l'impuls únic creat per la combinació del naixement de la televisió digital al Brasil i la creació del programa Brasil CI pel govern brasiler. Sense esta combinació no hauria estat possible realitzar este tipus de projectes a Brasil. Estos projectes han suposat un viatge llarg i costós, tot i que digne científicament i tecnològica, cap a un circuit integrat punter de baixa complexitat per a la TDT brasilera, amb bones perspectives d'economia d'escala perquè a l'inici d'este projecte l'estàndard ISDB-T no va ser adoptat per diversos països, com el DVB-T. Durant el desenvolupament del receptor de ISDB-T proposat en esta tesi, va resultar que, a causa de les dimensions continentals de Brasil, la DTTB no seria suficient per cobrir tot el país amb el senyal de TDT oberta, especialment pel que fa a les localitzacions remotes allunyades de les regions d'alta densitat urbana.. En este moment, l'Institut de Recerca Eldorado i Idea! Sistemes Electrònics van preveure que, en un futur pròxim, no hi hauria a Brasil un sistema de distribució oberta de TDT d'alta definició a través de satèl¿lit. D'acord amb això, l'Institut de Recerca Eldorado va decidir que seria necessari crear un nou ASIC per a la recepció de radiodifusió per satèl¿lit. basat en l'estàndard DVB-S2. En esta tesi s'analitza en detall l'arquitectura i els algorismes proposats per l'execució d'un receptor ISDB-T de Freqüència Intermèdia (FI) de baixa complexitat sobre CMOS de Circuit Integrat d'Aplicacions Específiques (ASIC). L'arquitectura ací proposada es basa molt en l'algorisme de l'Ordinador Digital de Rotació de Coordenades (CORDIC), que és un algorisme simple i eficient adequat per implementacions VLSI. El receptor fa front a les deficiències inherents a la transmissió de canals sense fil i els cristalls del receptor. Esta tesi també analitza la metodologia adoptada i presenta els resultats de l'execució. Es presenta el rendiment del receptor i es compara amb els obtinguts per mitjà de simulacions. D'altra banda, esta tesi també presenta l'arquitectura i els algorismes d'un receptor de DVB-S2 de cara a la seua implementació en ASIC. No obstant això, a diferència del receptor ISDB-T, només s'introdueixen resultats preliminars d'implementació en ASIC. Això es va fer principalment amb la finalitat de tenir una estimació primerenca de la zona de dau per demostrar que el projecte en ASIC és econòmicament viable, així com per verificar possibles errors en l'etapa primerenca. Com en el cas del receptor ISDB-T, este receptor es basa molt en l'algorisme CORDIC i va ser un prototip de FPGA. La metodologia utilitzada per al segon receptor es deriva de la utilitzada per al receptor IRodrigues De Lima, E. (2016). Architecture and algorithms for the implementation of digital wireless receivers in FPGA and ASIC: ISDB-T and DVB-S2 cases [Tesis doctoral no publicada]. Universitat Politècnica de València. https://doi.org/10.4995/Thesis/10251/61967TESI

The Fifth NASA Symposium on VLSI Design

The fifth annual NASA Symposium on VLSI Design had 13 sessions including Radiation Effects, Architectures, Mixed Signal, Design Techniques, Fault Testing, Synthesis, Signal Processing, and other Featured Presentations. The symposium provides insights into developments in VLSI and digital systems which can be used to increase data systems performance. The presentations share insights into next generation advances that will serve as a basis for future VLSI design

SISTEM TV DIGITAL DAN PROSPEKNYA DI INDONESIA

Media penyiaran TV merupakan sarana penyampaian informasi yang efisien dan banyak digunakan di Indonesia maupun negara lainnya di dunia. Pada saat ini jumlah penyelenggara siaran TV nasional di Indonesia ada 11 stasiun yang terdiri dari 1 lembaga penyiaran TV publik yaitu TVRI dan 10 lembaga penyiaran TV swasta yaitu ANTV (Anteve) ,Global TV (TVG), Indosiar, Lativi, Metro TV, RCTI, SCTV, TPI, Trans TV dan TV7. Disamping penyelenggara siaran TV nasional di Indonesia juga terdapat kurang lebih 70 an lebih penyelenggara siaran TV lokal atau daerah. Dengan komposisi lembaga penyiaran TV seperti yang dijelaskan diatas, diperkirakan di Indonesia mempunyai jumlah pemirsa TV sebesar 40 juta orang, hal tersebut merupakan pangsa pasar yang cukup besar dan menarik bagi para operator TV untuk melakukan peningkatan investasi di dunia penyiaran TV. Para operator dalam melakukan peningkatan investasi di bidang penyiaran TV tentunya perlu untuk mengetahui parameter-parameter yang strategis misalnya pada pemilihan teknologi penyiaran TV agar investasi yang dilakukan bisa meningkatkan nilai tambah bagi pemirsa maupun operator itu sendiri. Perkembangan teknologi penyiaran TV terrestial (dari darat ke darat) baik yang digunakan untuk permirsa diam (fixed) dan pemirsa bergerak (mobile) mengalami perkembangan yang cukup pesat seiring dengan berkembangnya teknologi digital. Saat ini berbagai negara telah memutuskan untuk migrasi dari teknologi penyiaran TV analog ke teknologi penyiaran TV digital. Mengapa hal tersebut dilakukan, dikarenakan penyiaran TV terrestial dengan menggunakan teknologi digital mempunyai banyak keunggulan dibandingkan dengan penyiaran TV dengan teknologi analog. Saat ini, terdapat beberapa standard teknologi penyiaran TV digital yang telah digunakan antara lain Digital Video Broadcasting Terrestial (DVB-T) dari Eropa, Integrated Service Digital Broadcasting Terrestial (ISDB-T) dari Jepang, Advanced Television Systems Committee (ATSC) dari Amerika Serikat, Terrestrial-Digital Multimedia Broadcasting (T-DMB) dari Korea Selatan, Digital Multimedia Broadcasting Terrestrial (DMB-T) dari China. Meskipun pemerintah Indonesia telah menentukan akan menggunakan teknologi penyiaran TV Digital DVB-T, maka dengan mengetahui perbandingan masing-masing keunggulan teknologinya dan pengalaman masing-masing negara dalam mengimplementasikannya, akan banyak membantu dalam membuat perencanaan yang lebih matang dan menyeluruh untuk implementasi penyiaran TV digital di Indonesia. Hal itu akan mendatangkan nilai tambah yang sangat bermanfaat bagi operator, konsumen dan regulator. Munculnya paradigma konvergensi dengan meleburnya teknologi telekomunikasi dan teknologi informasi mengakibatkan penyiaran suara dan gambar bergerak dapat dinikmati oleh pemirsa dengan berbagai perangkat dari yang berukuran kecil sampai yang berukuran besar, demikian juga dari perangkat yang diam sampai yang bergerak. Hal tersebut mengakibatkan model bisnis penyiaran TV akan mengalami perubahan juga, mulai dari infrastruktur jaringan, konten penyiaran, perangkat penyiaran, serta regulasipun juga harus disesuaikan baik untuk pengaturan frekuensi dan operasionalnya serta standardisasi perangkat. Agar tidak menimbulkan berbagai permasalahan pada saat melakukan implementasi penyiaran TV digital, diperlukan pengetahuan yang memadai untuk menyusun langkah-langkah yang cukup strategi yang bertujuan untuk mendorong kemajuan industri lokal di Indonesia. Untuk uraian tentang tiga hal diatas seperti apa saja parameter strategis dalam peningkatan investasi dalam penyiaran TV, bagaimana perencanaan yang komprehensif untuk sistem dan teknologi penyiaran TV digital dan bagaimana cara penyusunan langkah strategis pada saat dilakukan migrasi ke penyiaran TV digital. Kesemuanya tersebut telah dijelaskan dalam buku ini secara rapi dan teratur, oleh karena itu dengan membaca buku ini, para pembaca akan mendapatkan berbagai informasi yang menyeluruh tentang penyiaran TV digital terrestial. Maka agar memudahkan pembaca dalam melakukan ekplorasi, buku ini diorganisasikan sebagai berikut : BAB I berisi tentang uraian tentang sejarah penyiaran TV di dunia dan di Indonesia, serta keunggulan teknologi penyiaran TV digital, hal ini dimaksudkan agar para pembaca buku ini dapat memperoleh gambaran singkat tentang karakteristik penyiaran TV analog dan penyiaran TV digital di Indonesia. Untuk mengetahui secara menyeluruh tentang beberapa teori teknologi digital pada penyiaran TV maka BAB II dalam buku ini telah memberikan penjelasan yang cukup detil, hal tersebut dimaksudkan untuk memberikan pembekalan pada pembaca agar dapat dengan mudah mengerti penjelasan tentang teknologi penyiaran TV digital beserta perbandingannya. Penjelasan tentang karakteristik teknologi penyiaran TV digital terrestial yang saat ini sedang berkembang telah diuraikan pada BAB III dan BAB IV BAB V akan berisi penjelasan tentang teknik pengukuran dan parameter pengukuran serta perangkat pengukuran yang dibutuhkan saat implementasi penyiaran TV digital, selain itu ditunjukan juga beberapa hasil pengukuran di Amerika, dan Brasil, serta hasil pengukuran di Indonesia saat ujicoba penyiaran TV digital di Jakarta. Hal ini dimaksudkan agar pembaca dapat mengetahui konsep perencanaan jaringan penyiaran TV digital. BAB VI, BAB VII dan BAB VIII akan menitik beratkan tentang perubahan model bisnis yang terjadi saat migrasi ke penyiaran TV digital yang dimulai dengan penjelasan tentang konvergensi, dilanjutkan dengan informasi migrasi penyiaran TV digital pada berbagai negara dan ditutup dengan uraian peluang dan tantangannya di Indonesia. Sebagai penutup editorial ini, saat ini banyak keinginan dan harapan dari berbagai komponen masyarakat seperti operator TV, regulator dan konsumer untuk migrasi ke penyiaran TV digital, adanya buku ini diharapkan tiga komponen tersebut mempunyai persepsi yang sama dan pengetahuan yang seimbang tentang teknologi penyiaran TV digital beserta prospek dan peluangnya, sehingga migrasi ke penyiaran TV digital di Indonesia menjadi mulus dengan kendala seminimal mungkin sesuai dengan harapan yang diinginkan

Continuous-Time and Companding Digital Signal Processors Using Adaptivity and Asynchronous Techniques

The fully synchronous approach has been the norm for digital signal processors (DSPs) for many decades. Due to its simplicity, the classical DSP structure has been used in many applications. However, due to its rigid discrete-time operation, a classical DSP has limited efficiency or inadequate resolution for some emerging applications, such as processing of multimedia and biological signals. This thesis proposes fundamentally new approaches to designing DSPs, which are different from the classical scheme. The defining characteristic of all new DSPs examined in this thesis is the notion of "adaptivity" or "adaptability." Adaptive DSPs dynamically change their behavior to adjust to some property of their input stream, for example the rate of change of the input. This thesis presents both enhancements to existing adaptive DSPs, as well as new adaptive DSPs. The main class of DSPs that are examined throughout the thesis are continuous-time (CT) DSPs. CT DSPs are clock-less and event-driven; they naturally adapt their activity and power consumption to the rate of their inputs. The absence of a clock also provides a complete avoidance of aliasing in the frequency domain, hence improved signal fidelity. The core of this thesis deals with the complete and systematic design of a truly general-purpose CT DSP. A scalable design methodology for CT DSPs is presented. This leads to the main contribution of this thesis, namely a new CT DSP chip. This chip is the first general-purpose CT DSP chip, able to process many different classes of CT and synchronous signals. The chip has the property of handling various types of signals, i.e. various different digital modulations, both synchronous and asynchronous, without requiring any reconfiguration; such property is presented for the first time CT DSPs and is impossible for classical DSPs. As opposed to previous CT DSPs, which were limited to using only one type of digital format, and whose design was hard to scale for different bandwidths and bit-widths, this chip has a formal, robust and scalable design, due to the systematic usage of asynchronous design techniques. The second contribution of this thesis is a complete methodology to design adaptive delay lines. In particular, it is shown how to make the granularity, i.e. the number of stages, adaptive in a real-time delay line. Adaptive granularity brings about a significant improvement in the line's power consumption, up to 70% as reported by simulations on two design examples. This enhancement can have a direct large power impact on any CT DSP, since a delay line consumes the majority of a CT DSP's power. The robust methodology presented in this thesis allows safe dynamic reconfiguration of the line's granularity, on-the-fly and according to the input traffic. As a final contribution, the thesis also examines two additional DSPs: one operating the CT domain and one using the companding technique. The former operates only on level-crossing samples; the proposed methodology shows a potential for high-quality outputs by using a complex interpolation function. Finally, a companding DSP is presented for MPEG audio. Companding DSPs adapt their dynamic range to the amplitude of their input; the resulting can offer high-quality outputs even for small inputs. By applying companding to MPEG DSPs, it is shown how the DSP distortion can be made almost inaudible, without requiring complex arithmetic hardware

Predictable embedded multiprocessor architecture for streaming applications

The focus of this thesis is on embedded media systems that execute applications from the application domain car infotainment. These applications, which we refer to as jobs, typically fall in the class of streaming, i.e. they process on a stream of data. The jobs are executed on heterogeneous multiprocessor platforms, for performance and power efficiency reasons. Most of these jobs have firm real-time requirements, like throughput and end-to-end latency. Car-infotainment systems become increasingly more complex, due to an increase in the supported number of jobs and an increase of resource sharing. Therefore, it is hard to verify, for each job, that the realtime requirements are satisfied. To reduce the verification effort, we elaborate on an architecture for a predictable system from which we can verify, at design time, that the job’s throughput and end-to-end latency requirements are satisfied. This thesis introduces a network-based multiprocessor system that is predictable. This is achieved by starting with an architecture where processors have private local memories and execute tasks in a static order, so that the uncertainty in the temporal behaviour is minimised. As an interconnect, we use a network that supports guaranteed communication services so that it is guaranteed that data is delivered in time. The architecture is extended with shared local memories, run-time scheduling of tasks, and a memory hierarchy. Dataflow modelling and analysis techniques are used for verification, because they allow cyclic data dependencies that influence the job’s performance. Shown is how to construct a dataflow model from a job that is mapped onto our predictable multiprocessor platforms. This dataflow model takes into account: computation of tasks, communication between tasks, buffer capacities, and scheduling of shared resources. The job’s throughput and end-to-end latency bounds are derived from a self-timed execution of the dataflow graph, by making use of existing dataflow-analysis techniques. It is shown that the derived bounds are tight, e.g. for our channel equaliser job, the accuracy of the derived throughput bound is within 10.1%. Furthermore, it is shown that the dataflow modelling and analysis techniques can be used despite the use of shared memories, run-time scheduling of tasks, and caches

Implementation of a VLC HDTV Distribution System for Consumer Premises

A unidirectional, visible light communication (VLC) system intended for the distribution of Digital Video Broadcasting (DVB), high-definition television (HDTV) content to DVB compatible TVs within consumer premises is presented. The system receives off-air HDTV content through a consumer grade DVB-T/T2 terrestrial set-top-box (STB) and re-encodes its Moving Picture Experts Group (MPEG) transport stream (TS) using a pulse position modulation (PPM) scheme called inversion offset PPM (IOPPM). The re-encoded TS is used to intensity modulate (IM) a blue light-emitting diode (LED) operating at a wavelength of 470 nm. Directed line-of-sight (DLOS) transmission is used over a free-space optical (FSO) channel exhibiting a Gaussian impulse response. A direct-detection (DD) receiver is used to detect the transmitted IOPPM stream, which is then decoded to recover the original MPEG TS. A STB supporting a high-definition multimedia interface (HDMI) is used to decode the MPEG TS and enable connectivity to an HD monitor. The system is presented as a complementary or an alternative distribution system to existing Wi-Fi and power-line technologies. VLC connectivity is promoted as a safer, securer, unlicensed and unregulated approach. The system is intended to enable TV manufacturers to reduce costs by, firstly, relocating the TV’s region specific radio frequency (RF) tuner and demodulator blocks to an external STB capable of supporting DVB reception standards, and, secondly, by eliminating all input and output connectors interfaces from the TV. Given the current trend for consumers to wall-mount TVs, the elimination of all connector interfaces, except the power cable, makes mounting simpler and easier. The operation of the final system was verified using real-world, off-air broadcast DVB-T/T2 channels supporting HDTV content. A serial optical transmission at a frequency of 66 MHz was achieved. The system also achieved 60 Mbit/s, error free transmission over a distance of 1.2 m without using error correction techniques. The methodology used to realise the system was a top-down, modular approach. Results were obtained from electrical modelling, simulation and experimental techniques, and using time-domain and FFT based measurements and analysis. The modular approach was adopted to enable design, development and testing of the subsystems independently of the overall system