A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio

Low-Voltage High-Linearity Wideband Current Differencing Transconductance Amplifier and Its Application on Current-Mode Active Filter

A low-voltage high-linearity wideband current differencing transconductance amplifier (CDTA) is presented in this paper. The CDTA consists of a current differencing circuit and a cross-coupling transconductance circuit. The PSPICE simulations of the proposed CDTA show a good performance: -3dB frequency bandwith is about 900 MHz, low power consumption is 2.48 mW, input current linear range is ±100 µA and low current-input resistance is less than 20 Ω, high current-output resistance is more than 3 MΩ. PSpice simulations for a current-mode universal filter and a proposed high-order filter are also conducted, and the results verify the validity of the proposed CDTA

Digital PLL for ISM applications

In modern transceivers, a low power PLL is a key block. It is known that with the evolution of technology, lower power and high performance circuitry is a challenging demand. In this thesis, a low power PLL is developed in order not to exceed 2mW of total power consumption. It is composed by small area blocks which is one of the main demands. The blocks that compose the PLL are widely abridged and the final solution is shown, showing why it is employed. The VCO block is a Current-Starved Ring Oscillator with a frequency range from 400MHz to 1.5GHz, with a 300μW to approximately 660μW power consumption. The divider is composed by six TSPC D Flip-Flop in series, forming a divide-by-64 divider. The Phase-Detector is a Dual D Flip-Flop detector with a charge pump. The PLL has less than a 2us lock time and presents a output oscillation of 1GHz, as expected. It also has a total power consumption of 1.3mW, therefore fulfilling all the specifications. The main contributions of this thesis are that this PLL can be applied in ISM applications due to its covering frequency range and low cost 130nm CMOS technology

A precise 90º quadrature OTA-C oscillator tunable in the 50-130-MHz range

We present a very-large-scale integration continuous-time sinusoidal operational transconductance amplifiers quadrature oscillator fabricated in a standard double-poly 0.8-μm CMOS process. The oscillator is tunable in the frequency range from 50 to 130 MHz. The two phases produced by the oscillator show a low-quadrature phase error. A novel current-mode amplitude control scheme is developed that allows for very small amplitudes. Stability of the amplitude control loop is studied as well as design considerations for its optimization. Experimental results are provided

8-Phase Ring oscillator for modern receivers

The evolution of receiver architectures, built in modern CMOS technologies, allows the design of high efficient receivers. A key block in modern receivers is the oscillator. The main objective of this thesis is to design a very low power and low area 8-Phase Ring Oscillator for biomedical applications (ISM and WMTS bands). Oscillators with multiphase outputs and variable duty cycles are required. In this thesis we are focused in 12.5% and 50% duty-cycles approaches. The proposed circuit uses eight inverters in a ring structure, in order to generate the output duty cycle of 50%. The duty cycle of 1/8 is achieved through the combination of the longer duty cycle signals in pairs, using, for this purpose, NAND gates. Since the general application are not only the wireless communications context, as well as industrial, scientific and medical plans, the 8-Phase Oscillator is simulated to be wideband between 100 MHz and 1 GHz, and be able to operate in the ISM bands (447 MHz-930 MHz) and WMTS (600 MHz). The circuit prototype is designed in UMC 130 nm CMOS technology. The maximum value of current drawn from a DC power source of 1.2 V, at a maximum frequency of 930 MHz achieved, is 17.54 mA. After completion of the oscillator layout studied (occupied area is 165 μm x 83 μm). Measurement results confirm the expected operating range from the simulations, and therefore, that the oscillator fulfil effectively the goals initially proposed in order to be used as Local Oscillator in RF Modern Receivers

Circuits for Analog Signal Processing Employing Unconventional Active Elements

Disertační práce se zabývá zaváděním nových struktur moderních aktivních prvků pracujících v napěťovém, proudovém a smíšeném režimu. Funkčnost a chování těchto prvků byly ověřeny prostřednictvím SPICE simulací. V této práci je zahrnuta řada simulací, které dokazují přesnost a dobré vlastnosti těchto prvků, přičemž velký důraz byl kladen na to, aby tyto prvky byly schopny pracovat při nízkém napájecím napětí, jelikož poptávka po přenosných elektronických zařízeních a implantabilních zdravotnických přístrojích stále roste. Tyto přístroje jsou napájeny bateriemi a k tomu, aby byla prodloužena jejich životnost, trend navrhování analogových obvodů směřuje k stále většímu snižování spotřeby a napájecího napětí. Hlavním přínosem této práce je návrh nových CMOS struktur: CCII (Current Conveyor Second Generation) na základě BD (Bulk Driven), FG (Floating Gate) a QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) na základě FG, transkonduktor na základě nové techniky BD_QFG (Bulk Driven_Quasi Floating Gate), CCCDBA (Current Controlled Current Differencing Buffered Amplifier) na základě GD (Gate Driven), VDBA (Voltage Differencing Buffered Amplifier) na základě GD a DBeTA (Differential_Input Buffered and External Transconductance Amplifier) na základě BD. Dále je uvedeno několik zajímavých aplikací užívajících výše jmenované prvky. Získané výsledky simulací odpovídají teoretickým předpokladům.The dissertation thesis deals with implementing new structures of modern active elements working in voltage_, current_, and mixed mode. The functionality and behavior of these elements have been verified by SPICE simulation. Sufficient numbers of simulated plots are included in this thesis to illustrate the precise and strong behavior of those elements. However, a big attention to implement active elements by utilizing LV LP (Low Voltage Low Power) techniques is given in this thesis. This attention came from the fact that growing demand of portable electronic equipments and implantable medical devices are pushing the development towards LV LP integrated circuits because of their influence on batteries lifetime. More specifically, the main contribution of this thesis is to implement new CMOS structures of: CCII (Current Conveyor Second Generation) based on BD (Bulk Driven), FG (Floating Gate) and QFG (Quasi Floating Gate); DVCC (Differential Voltage Current Conveyor) based on FG; Transconductor based on new technique of BD_QFG (Bulk Driven_Quasi Floating Gate); CCCDBA (Current Controlled Current Differencing Buffered Amplifier) based on conventional GD (Gate Driven); VDBA (Voltage Differencing Buffered Amplifier) based on GD. Moreover, defining new active element i.e. DBeTA (Differential_Input Buffered and External Transconductance Amplifier) based on BD is also one of the main contributions of this thesis. To confirm the workability and attractive properties of the proposed circuits many applications were exhibited. The given results agree well with the theoretical anticipation.

Low frequency sinusoidal oscillator for impedance spectroscopy

textImpedance measurement as a function of frequency is being increasingly used for the detection of organic molecules. The main building block required for this is a sinusoidal oscillator whose frequency can be varied in the range of a few KHz to tens of MHz. The thesis describes the design of Integrated CMOS Oscillator Circuits. There are 2 designs presented in the thesis, one of which is based on the Wien Bridge and the other, on an LC architecture. They provide both in-phase and quadrature outputs needed for the determination of the real and imaginary parts of complex impedances. The inductor in the LC tank is realized by gyration of a capacitor. This needs two variable transconductance elements. Linear transconductance elements with decoupled transconductance gm and output conductance go is presented. A novel circuit for detecting and controlling the amplitude of oscillation is described. A current mode technique to scale the capacitance is also discussed. Since this oscillator is used in an inexpensive hand-held instrument, both power consumption and chip area must be minimized. A comparison between the Wien Bridge and the LC tank based oscillator is presented. Simulation results pertaining to the design of the different blocks of the circuit are made available.Electrical and Computer Engineerin

Low-power transceiver design for mobile wireless chemical biological sensors

The design of a smart integrated chemical sensor system that will enhance sensor performance and compatibility to Ad hoc network architecture remains a challenge. This work involves the design of a Transceiver for a mobile chemical sensor. The transceiver design integrates all building blocks on-chip, including a low-noise amplifier with an input-matching network, a Voltage Controlled Oscillator with injection locking, Gilbert cell mixers, and a Class E Power amplifier making it as a single-chip transceiver. This proposed low power 2GHz transceiver has been designed in TSMC 0.35~lm CMOS process using Cadence electronic design automation tools. Post layout HSPICE simulation indicates that Design meets the separation of noise levels by 52dB and 42dB in transmitter and receiver respectively with power consumption of 56 mW and 38 mW in transmit and receive mode

Low power low voltage quadrature RC oscillators for modern RF receivers

Dissertação apresentada na Faculdade de Ciências e Tecnologia da Universidade Nova de Lisboa para a obtenção do grau de Mestre em Engenharia Electrotécnica e de ComputadoresThis thesis proposes a study of three different RC oscillators, two relaxation and a ring oscillator. All the circuits are implemented using UMC 130 nm CMOS technology with a supply voltage of 1.2 V. We present a wideband MOS current/voltage controlled quadrature oscillator constituted by two multivibrators. Two different forms of coupling named, soft (traditional)and hard (proposed) are differentiated and investigated. It is found that hard coupling reduces the quadrature error and results in a low phase-noise (about 2 dB improvement) with respect to soft coupling. The behaviour of the singular and coupled multivibrators is investigated, when an external synchronizing harmonic is applied. We introduce a new RC relaxation oscillator with pulse self biasing, to reduce power consumption, and with harmonic ltering and resistor feedback, to reduce phase-noise. The designed circuit has a very low phase-noise, -132.6 dBc/Hz @ 10 MHz offset, and the power consumption is only 1 mW, which leads to a gure of merit (FOM) of -159.1 dBc/Hz. The nal circuit is a two integrator fully implemented in CMOS technology, with low power consumption. The respective layout is made and occupies a total area of5.856x10-3 mm2, post-layout simulation is also done

Low-Voltage Ultra-Low-Power Current Conveyor Based on Quasi-Floating Gate Transistors

The field of low-voltage low-power CMOS technology has grown rapidly in recent years; it is an essential prerequisite particularly for portable electronic equipment and implantable medical devices due to its influence on battery lifetime. Recently, significant improvements in implementing circuits working in the low-voltage low-power area have been achieved, but circuit designers face severe challenges when trying to improve or even maintain the circuit performance with reduced supply voltage. In this paper, a low-voltage ultra-low-power current conveyor second generation CCII based on quasi-floating gate transistors is presented. The proposed circuit operates at a very low supply voltage of only ±0.4 V with rail-to-rail voltage swing capability and a total quiescent power consumption of mere 9.5 µW. Further, the proposed circuit is not only able to process the AC signal as it's usual at quasi-floating gate transistors but also the DC which extends the applicability of the proposed circuit. In conclusion, an application example of the current-mode quadrature oscillator is presented. PSpice simulation results using the 0.18 µm TSMC CMOS technology are included to confirm the attractive properties of the proposed circuit