Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

Ultra-low power mixed-signal frontend for wearable EEGs

Electronics circuits are ubiquitous in daily life, aided by advancements in the chip design industry, leading to miniaturised solutions for typical day to day problems. One of the critical healthcare areas helped by this advancement in technology is electroencephalography (EEG). EEG is a non-invasive method of tracking a person's brain waves, and a crucial tool in several healthcare contexts, including epilepsy and sleep disorders. Current ambulatory EEG systems still suffer from limitations that affect their usability. Furthermore, many patients admitted to emergency departments (ED) for a neurological disorder like altered mental status or seizures, would remain undiagnosed hours to days after admission, which leads to an elevated rate of death compared to other conditions. Conducting a thorough EEG monitoring in early-stage could prevent further damage to the brain and avoid high mortality. But lack of portability and ease of access results in a long wait time for the prescribed patients. All real signals are analogue in nature, including brainwaves sensed by EEG systems. For converting the EEG signal into digital for further processing, a truly wearable EEG has to have an analogue mixed-signal front-end (AFE). This research aims to define the specifications for building a custom AFE for the EEG recording and use that to review the suitability of the architectures available in the literature. Another critical task is to provide new architectures that can meet the developed specifications for EEG monitoring and can be used in epilepsy diagnosis, sleep monitoring, drowsiness detection and depression study. The thesis starts with a preview on EEG technology and available methods of brainwaves recording. It further expands to design requirements for the AFE, with a discussion about critical issues that need resolving. Three new continuous-time capacitive feedback chopped amplifier designs are proposed. A novel calibration loop for setting the accurate value for a pseudo-resistor, which is a crucial block in the proposed topology, is also discussed. This pseudoresistor calibration loop achieved the resistor variation of under 8.25%. The thesis also presents a new design of a curvature corrected bandgap, as well as a novel DDA based fourth-order Sallen-Key filter. A modified sensor frontend architecture is then proposed, along with a detailed analysis of its implementation. Measurement results of the AFE are finally presented. The AFE consumed a total power of 3.2A (including ADC, amplifier, filter, and current generation circuitry) with the overall integrated input-referred noise of 0.87V-rms in the frequency band of 0.5-50Hz. Measurement results confirmed that only the proposed AFE achieved all defined specifications for the wearable EEG system with the smallest power consumption than state-of-art architectures that meet few but not all specifications. The AFE also achieved a CMRR of 131.62dB, which is higher than any studied architectures.Open Acces

A Low Power Low Noise Instrumentation Amplifier For ECG Recording Applications

The instrumentation amplifier (IA) is one of the crucial blocks in an electrocardiogram recording system. It is the first block in the analog front-end chain that processes the ECG signal from the human body and thus it defines some of the most important specifications of the ECG system like the noise and common mode rejection ratio (CMRR). The extremely low ECG signal bandwidth also makes it difficult to achieve a fully integrated system. In this thesis, a fully integrated IA topology is presented that achieves low noise levels and low power dissipation. The chopper stabilized technique is implemented together with an AC coupled amplifier to reduce the effect of flicker noise while eliminating the effect of the differential electrode offset (DEO). An ultra low power operational transconductance amplifier (OTA) is the only active power consuming block in the IA and so an overall low power consumption is achieved. A new implementation of a large resistor using the T-network is presented which makes it easy to achieve a fully integrated solution. The proposed IA operates on a 2V supply and consumes a total current of 1.4µA while achieving an integrated noise of 1.2µVrms within the bandwidth. The proposed IA will relax the power and noise requirements of the analog-to-digital converter (ADC) that immediately follows it in the signal chain and thus reduce the cost and increase the lifetime of the recording device. The proposed IA has been implemented in the ONSEMI 0.5µm CMOS technology

Current-efficient preamplifier architecture for CMRR sensitive neural recording applications

Este trabajo fue parcialmente financiado por CSIC (Comisión Sectorial de Investigación Científica, Uruguay), ANII (Agencia Nacional de Investigación e Innovación, Uruguay) y CAP (Comisión Académica de Posgrado, Uruguay).There are neural recording applications in which the amplitude of common-mode interfering signals is several orders of magnitude higher than the amplitude of the signals of interest. This challenging situation for neural amplifiers occurs, among other applications, in neural recordings of weakly electric fish or nerve activity recordings made with cuff electrodes. This paper reports an integrated neural amplifier architecture targeting invivo recording of local field potentials and unitary signals from the brain stem of a weakly electric fish Gymnotus omarorum. The proposed architecture offers low noise, high common-mode rejection ratio (CMRR), current-efficiency, and a high-pass frequency fixed without MOS pseudoresistors. The main contributions of this work are the overall architecture coupled with an efficient and simple single-stage circuit for the amplifier main transconductor, and the ability of the amplifier to acquire biopotential signals from high-amplitude common-mode interference in an unshielded environment. A fully-integrated neural preamplifier, which performs well in line with the state-of-the-art of the field while providing enhanced CMRR performance, was fabricated in a 0.5 μm CMOS process. Results from measurements show that the gain is 49.5 dB, the bandwidth ranges from 13 Hz to 9.8 kHz, the equivalent input noise is 1.88 μVrms, the CMRR is 87 dB and the Noise Efficiency Factor is 2.1. In addition, in-vivo recordings of weakly electric fish neural activity performed by the proposed amplifier are introduced and favorably compared with those of a commercial laboratory instrumentation system

Amplifiers in Biomedical Engineering: A Review from Application Perspectives

Continuous monitoring and treatment of various diseases with biomedical technologies and wearable electronics has become significantly important. The healthcare area is an important, evolving field that, among other things, requires electronic and micro-electromechanical technologies. Designed circuits and smart devices can lead to reduced hospitalization time and hospitals equipped with high-quality equipment. Some of these devices can also be implanted inside the body. Recently, various implanted electronic devices for monitoring and diagnosing diseases have been presented. These instruments require communication links through wireless technologies. In the transmitters of these devices, power amplifiers are the most important components and their performance plays important roles. This paper is devoted to collecting and providing a comprehensive review on the various designed implanted amplifiers for advanced biomedical applications. The reported amplifiers vary with respect to the class/type of amplifier, implemented CMOS technology, frequency band, output power, and the overall efficiency of the designs. The purpose of the authors is to provide a general view of the available solutions, and any researcher can obtain suitable circuit designs that can be selected for their problem by reading this survey

A 122 fps, 1 MHz bandwidth multi-frequency wearable EIT belt featuring novel active electrode architecture for neonatal thorax vital sign monitoring

A highly integrated, wearable electrical impedance tomography (EIT) belt for neonatal thorax vital multiple sign monitoring is presented. The belt has sixteen active electrodes. Each has an application specific integrated circuit (ASIC) connected to an electrode. The ASIC contains a fully differential current driver, a high-performance instrumentation amplifier (IA), a digital controller and multiplexors. The wearable EIT belt features a new active electrode architecture that allows programmable flexible electrode current drive and voltage sense patterns under simple digital control. It provides intimate connections to the electrodes for the current drive and to the IA for direct differential voltage measurement providing superior common-mode rejection ratio. The ASIC was designed in a CMOS 0.35-μm high-voltage technology. The high specification EIT belt has an image frame rate of 122 fps, a wide operating bandwidth of 1 MHz and multi-frequency operation. It measures impedance with 98% accuracy and has less than 0.5 Ω and 1o variation across all possible channels. The image results confirmed the advantage of the new active electrode architecture and the benefit of wideband, multi-frequency EIT operation. The wearable EIT belt can also detect patient position and torso shape information using a MEMS sensor interfaced to each ASIC. The system successfully captured high quality lung respiration EIT images, breathing cycle and heart rate

A low power low voltage biomedical signal acquisition chip

Master'sMASTER OF ENGINEERIN

Proof of Principle of an On-Line Digitizer with +18 ppm Repeatability and 1.2 μs Real-Time Delay for Power Converters Control Loop

The proof of principle of an on-line digitizer designed to be integrated into the digital control loop of a high-voltage modulator for ultra-repeatable power converters is presented. The presented selective analogue zoom allows digitizing with 18 ppm repeatability the voltage around the nominal level (10V1 V) and, at the same time, the initial transients with relaxed performance. In addition, in order not to jeopardize the digital control loop stability, the whole digitizing system has to introduce a low real-time delay; this is assessed to be less than 1:2 s. Initially, the specifications of the real-time control are presented and translated into data acquisition requirements. Then, the main design choices of the digitizer are discussed and Pspice simulation results are reported to validate the concept design. Finally, experimental results of a validation case study developed for the power converter designed at ETH Zurich and University of Laval for the new linear particle accelerator under study at CERN, the Compact LInear Collider CLIC, are reported and compared with the simulation outcomes