Modelling for optimisation of self-powered wireless sensor nodes

Accepted versio

Software controlled low cost thermoelectric energy harvester for ultra-low power wireless sensor nodes

General hardware architecture of an energy-harvested wireless sensor network node (EH-WSN) can be divided into power, sensing, computing and communication subsystems. Interrelation between these subsystems in combination with constrained energy supply makes design and implementation of EH-WSN a complex and challenging task. Separation of these subsystems into distinct hardware modules simplifies the design process and makes the architecture and software more generic, leading to more flexible solutions. From the other hand, tightly coupling these subsystems gives more room for optimizations at the price of increased complexity of the hardware and software. Additional engineering effort could be justified by a smaller, cheaper hardware, and more energy-efficient a wireless sensor node. The aim of this paper is to push further technical and economical boundaries related to EH-WSN by proposing a novel architecture which – by tightly coupling software and hardware of power, computing, and communication subsystems – allows the wireless sensor node to be powered by a thermoelectric generator working with about 1.5°C temperature difference while keeping the cost of all electronic components used to build such a node below 9 EUR (in volume)

Energy autonomous systems : future trends in devices, technology, and systems

The rapid evolution of electronic devices since the beginning of the nanoelectronics era has brought about exceptional computational power in an ever shrinking system footprint. This has enabled among others the wealth of nomadic battery powered wireless systems (smart phones, mp3 players, GPS, …) that society currently enjoys. Emerging integration technologies enabling even smaller volumes and the associated increased functional density may bring about a new revolution in systems targeting wearable healthcare, wellness, lifestyle and industrial monitoring applications

Adiabatic Approach for Low-Power Passive Near Field Communication Systems

This thesis tackles the need of ultra-low power electronics in the power limited passive Near Field Communication (NFC) systems. One of the techniques that has proven the potential of delivering low power operation is the Adiabatic Logic Technique. However, the low power benefits of the adiabatic circuits come with the challenges due to the absence of single opinion on the most energy efficient adiabatic logic family which constitute appropriate trade-offs between computation time, area and complexity based on the circuit and the power-clocking schemes. Therefore, five energy efficient adiabatic logic families working in single-phase, 2-phase and 4-phase power-clocking schemes were chosen. Since flip-flops are the basic building blocks of any sequential circuit and the existing flip-flops are MUX-based (having more transistors) design, therefore a novel single-phase, 2-phase and 4-phase reset based flip-flops were proposed. The performance of the multi-phase adiabatic families was evaluated and compared based on the design examples such as 2-bit ring counter, 3-bit Up-Down counter and 16-bit Cyclic Redundancy Check (CRC) circuit (benchmark circuit) based on ISO 14443-3A standard. Several trade-offs, design rules, and an appropriate range for the supply voltage scaling for multi-phase adiabatic logic are proposed. Furthermore, based on the NFC standard (ISO 14443-3A), data is frequently encoded using Manchester coding technique before transmitting it to the reader. Therefore, if Manchester encoding can be implemented using adiabatic logic technique, energy benefits are expected. However, adiabatic implementation of Manchester encoding presents a challenge. Therefore, a novel method for implementing Manchester encoding using adiabatic logic is proposed overcoming the challenges arising due to the AC power-clock. Other challenges that come with the dynamic nature of the adiabatic gates and the complexity of the 4-phase power-clocking scheme is in synchronizing the power-clock v phases and the time spent in designing, validation and debugging of errors. This requires a specific modelling approach to describe the adiabatic logic behaviour at the higher level of abstraction. However, describing adiabatic logic behaviour using Hardware Description Languages (HDLs) is a challenging problem due to the requirement of modelling the AC power-clock and the dual-rail inputs and outputs. Therefore, a VHDL-based modelling approach for the 4-phase adiabatic logic technique is developed for functional simulation, precise timing analysis and as an improvement over the previously described approaches

Development of a 0.6-MV ultracompact magnetic core pulsed transformer for high-power applications

The generation of high-power electromagnetic waves is one of the major applications in the field of high-intensity pulsed power. The conventional structure of a pulsed power generator contains a primary energy source and a load separated by a power-amplification system. The latter performs time compression of the slow input energy pulse and delivers a high-intensity power output to the load. Usually, either a Marx generator or a Tesla transformer is used as a power amplifier. In the present case, a system termed “module oscillant utilisant une nouvelle architecture” (MOUNA) uses an innovative and very compact resonant pulsed transformer to drive a dipole antenna. This paper describes the ultracompact multiprimary winding pulsed transformer developed in common by the Université de Pau and Hi Pulse Company that can generate voltage pulses of up to 0.6 MV, with a rise time of less than 270 ns. The transformer design has four primary windings, with two secondary windings in parallel, and a Metglas 2605SA1 amorphous iron magnetic core with an innovative biconic geometry used to optimize the leakage inductance. The overall unit has a weight of 6 kg and a volume of only 3.4 L, and this paper presents in detail its design procedure, with each of the main characteristics being separately analyzed. In particular, simple but accurate analytical calculations of both the leakage inductance and the stray capacitance between the primary and secondary windings are presented and successfully compared with CST-based results. Phenomena such as the core losses and saturation induction are also analyzed. The resonant power-amplifier output characteristics are experimentally studied when attached to a compact capacitive load, coupled to a capacitive voltage probe developed jointly with Loughborough University. Finally, an LTspice-based model of the power amplifier is introduced and its predictions are compared with results obtained from a thorough experimental study

Cryptography for Ultra-Low Power Devices

Ubiquitous computing describes the notion that computing devices will be everywhere: clothing, walls and floors of buildings, cars, forests, deserts, etc. Ubiquitous computing is becoming a reality: RFIDs are currently being introduced into the supply chain. Wireless distributed sensor networks (WSN) are already being used to monitor wildlife and to track military targets. Many more applications are being envisioned. For most of these applications some level of security is of utmost importance. Common to WSN and RFIDs are their severely limited power resources, which classify them as ultra-low power devices. Early sensor nodes used simple 8-bit microprocessors to implement basic communication, sensing and computing services. Security was an afterthought. The main power consumer is the RF-transceiver, or radio for short. In the past years specialized hardware for low-data rate and low-power radios has been developed. The new bottleneck are security services which employ computationally intensive cryptographic operations. Customized hardware implementations hold the promise of enabling security for severely power constrained devices. Most research groups are concerned with developing secure wireless communication protocols, others with designing efficient software implementations of cryptographic algorithms. There has not been a comprehensive study on hardware implementations of cryptographic algorithms tailored for ultra-low power applications. The goal of this dissertation is to develop a suite of cryptographic functions for authentication, encryption and integrity that is specifically fashioned to the needs of ultra-low power devices. This dissertation gives an introduction to the specific problems that security engineers face when they try to solve the seemingly contradictory challenge of providing lightweight cryptographic services that can perform on ultra-low power devices and shows an overview of our current work and its future direction