Design Techniques for High-Performance SAR A/D Converters

The design of electronics needs to account for the non-ideal characteristics of the device technologies used to realize practical circuits. This is particularly important in mixed analog-digital design since the best device technologies are very different for digital compared to analog circuits. One solution for this problem is to use a calibration correction approach to remove the errors introduced by devices, but this adds complexity and power dissipation, as well as reducing operation speed, and so must be optimised. This thesis addresses such an approach to improve the performance of certain types of analog-to-digital converter (ADC) used in advanced telecommunications, where speed, accuracy and power dissipation currently limit applications. The thesis specifically focuses on the design of compensation circuits for use in successive approximation register (SAR) ADCs. ADCs are crucial building blocks in communication systems, in general, and for mobile networks, in particular. The recently launched fifth generation of mobile networks (5G) has required new ADC circuit techniques to meet the higher speed and lower power dissipation requirements for 5G technology. The SAR has become one of the most favoured architectures for designing high-performance ADCs, but the successive nature of the circuit operation makes it difficult to reach ∼GS/s sampling rates at reasonable power consumption. Here, two calibration techniques for high-performance SAR ADCs are presented. The first uses an on-chip stochastic-based mismatch calibration technique that is able to accurately compute and compensate for the mismatch of a capacitive DAC in a SAR ADC. The stochastic nature of the proposed calibration method enables determination of the mismatch of the CAPDAC with a resolution much better than that of the DAC. This allows the unit capacitor to scale down to as low as 280aF for a 9-bit DAC. Since the CAP-DAC causes a large part of the overall dynamic power consumption and directly determines both the sizes of the driving and sampling switches and the size of the input capacitive load of the ADC and the kT/C noise power, a small CAP-DAC helps the power efficiency. To validate the proposed calibration idea, a 10-bit asynchronous SAR ADC was fabricated in 28-nm CMOS. Measurement results show that the proposed stochastic calibration improves the ADC’s SFDR and SNDR by 14.9 dB, 11.5 dB, respectively. After calibration, the fabricated SAR ADC achieves an ENOB of 9.14 bit at a sampling rate of 85 MS/s, resulting in a Walden FoM of 10.9 fJ/c-s. The second calibration technique is a timing-skew calibration for a time-interleaved (TI) SAR ADC that calibrates/computes the inter-channel timing and offset mismatch simultaneously. Simulation results show the effectiveness of this calibration method. When used together, the proposed mismatch calibration technique and the timing-skew calibration technique enables a TI SAR ADC to be designed that can achieve a sampling rate of ∼GS/s with 10-bit resolution and a power consumption as low as ∼10mW; specifications that satisfy the requirements of 5G technology

Concepts for smart AD and DA converters

This thesis studies the `smart' concept for application to analog-to-digital and digital-to-analog converters. The smart concept aims at improving performance - in a wide sense - of AD/DA converters by adding on-chip intelligence to extract imperfections and to correct for them. As the smart concept can correct for certain imperfections, it can also enable the use of more efficient architectures, thus yielding an additional performance boost. Chapter 2 studies trends and expectations in converter design with respect to applications, circuit design and technology evolution. Problems and opportunities are identfied, and an overview of performance criteria is given. Chapter 3 introduces the smart concept that takes advantage of the expected opportunities (described in chapter 2) in order to solve the anticipated problems. Chapter 4 applies the smart concept to digital-to-analog converters. In the discussed example, the concept is applied to reduce the area of the analog core of a current-steering DAC. It is shown that a sub-binary variable-radix approach reduces the area of the current-source elements substantially (10x compared to state-of-the-art), while maintaining accuracy by a self-measurement and digital pre-correction scheme. Chapter 5 describes the chip implementation of the sub-binary variable-radix DAC and discusses the experimental results. The results confirm that the sub-binary variable-radix design can achieve the smallest published current-source-array area for the given accuracy (12bit). Chapter 6 applies the smart concept to analog-to-digital converters, with as main goal the improvement of the overall performance in terms of a widely used figure-of-merit. Open-loop circuitry and time interleaving are shown to be key to achieve high-speed low-power solutions. It is suggested to apply a smart approach to reduce the effect of the imperfections, unintentionally caused by these key factors. On high-level, a global picture of the smart solution is proposed that can solve the problems while still maintaining power-efficiency. Chapter 7 deals with the design of a 500MSps open-loop track-and-hold circuit. This circuit is used as a test case to demonstrate the proposed smart approaches. Experimental results are presented and compared against prior art. Though there are several limitations in the design and the measurement setup, the measured performance is comparable to existing state-of-the-art. Chapter 8 introduces the first calibration method that counteracts the accuracy issues of the open-loop track-and-hold. A description of the method is given, and the implementation of the detection algorithm and correction circuitry is discussed. The chapter concludes with experimental measurement results. Chapter 9 introduces the second calibration method that targets the accuracy issues of time-interleaved circuits, in this case a 2-channel version of the implemented track-and-hold. The detection method, processing algorithm and correction circuitry are analyzed and their implementation is explained. Experimental results verify the usefulness of the method

A jittered-sampling correction technique for ADCs

In Analogue to Digital Converters (ADCs) jittered sampling raises the noise floor; this leads to a decrease in its Signal to Noise ratio (SNR) and its effective number of bits (ENOB). This research studies a technique that compensate for the effects of sampling with a jittered clock. A thorough understanding of sampling in various data converters is complied

Digital Background Self-Calibration Technique for Compensating Transition Offsets in Reference-less Flash ADCs

This Dissertation focusses on proving that background calibration using adaptive algorithms are low-cost, stable and effective methods for obtaining high accuracy in flash A/D converters. An integrated reference-less 3-bit flash ADC circuit has been successfully designed and taped out in UMC 180 nm CMOS technology in order to prove the efficiency of our proposed background calibration. References for ADC transitions have been virtually implemented built-in in the comparators dynamic-latch topology by a controlled mismatch added to each comparator input front-end. An external very simple DAC block (calibration bank) allows control the quantity of mismatch added in each comparator front-end and, therefore, compensate the offset of its effective transition with respect to the nominal value. In order to assist to the estimation of the offset of the prototype comparators, an auxiliary A/D converter with higher resolution and lower conversion speed than the flash ADC is used: a 6-bit capacitive-DAC SAR type. Special care in synchronization of analogue sampling instant in both ADCs has been taken into account. In this thesis, a criterion to identify the optimum parameters of the flash ADC design with adaptive background calibration has been set. With this criterion, the best choice for dynamic latch architecture, calibration bank resolution and flash ADC resolution are selected. The performance of the calibration algorithm have been tested, providing great programmability to the digital processor that implements the algorithm, allowing to choose the algorithm limits, accuracy and quantization errors in the arithmetic. Further, systematic controlled offset can be forced in the comparators of the flash ADC in order to have a more exhaustive test of calibration

Time-Interleaved Analog-to-Digital-Converters: Modeling, Blind Identification and Digital Correction of Frequency Response Mismatches

Analog-to-digital-conversion enables utilization of digital signal processing (DSP) in many applications today such as wireless communication, radar and electronic warfare. DSP is the favored choice for processing information over analog signal processing (ASP) because it can typically offer more flexibility, computational power, reproducibility, speed and accuracy when processing and extracting information. Software defined radio (SDR) receiver is one clear example of this, where radio frequency waveforms are converted into digital form as close to the antenna as possible and all the processing of the information contained in the received signal is extracted in a configurable manner using DSP. In order to achieve such goals, the information collected from the real world signals, which are commonly analog in their nature, must be converted into digital form before it can be processed using DSP in the respective systems. The common trend in these systems is to not only process ever larger bandwidths of data but also to process data in digital format at ever higher processing speeds with sufficient conversion accuracy. So the analog-to-digital-converter (ADC), which converts real world analog waveforms into digital form, is one of the most important cornerstones in these systems.The ADC must perform data conversion at higher and higher rates and digitize ever-increasing bandwidths of data. In accordance with the Nyquist-Shannon theorem, the conversion rate of the ADC must be suffcient to accomodate the BW of the signal to be digitized, in order to avoid aliasing. The conversion rate of the ADC can in general be increased by using parallel ADCs with each ADC performing the sampling at mutually different points in time. Interleaving the outputs of each of the individual ADCs provides then a higher digitization output rate. Such ADCs are referred to as TI-ADC. However, the mismatches between the ADCs cause unwanted spurious artifacts in the TI-ADC’s spectrum, ultimately leading to a loss in accuracy in the TI-ADC compared to the individual ADCs. Therefore, the removal or correction of these unwanted spurious artifacts is essential in having a high performance TI-ADC system.In order to remove the unwanted interleaving artifacts, a model that describes the behavior of the spurious distortion products is of the utmost importance as it can then facilitate the development of efficient digital post-processing schemes. One major contribution of this thesis consists of the novel and comprehensive modeling of the spurious interleaving mismatches in different TI-ADC scenarios. This novel and comprehensive modeling is then utilized in developing digital estimation and correction methods to remove the mismatch induced spurious artifacts in the TI-ADC’s spectrum and recovering its lost accuracy. Novel and first of its kind digital estimation and correction methods are developed and tested to suppress the frequency dependent mismatch spurs found in the TI-ADCs. The developed methods, in terms of the estimation of the unknown mismatches, build on statistical I/Q signal processing principles, applicable without specifically tailored calibration signals or waveforms. Techniques to increase the analog BW of the ADC are also analyzed and novel solutions are presented. The interesting combination of utilizing I/Q downconversion in conjunction with TI-ADC is examined, which not only extends the TI-ADC’s analog BW but also provides flexibility in accessing the radio spectrum. Unwanted spurious components created during the ADC’s bandwidth extension process are also analyzed and digital correction methods are developed to remove these spurs from the spectrum. The developed correction techniques for the removal of the undesired interleaving mismatch artifacts are validated and tested using various HW platforms, with up to 1 GHz instantaneous bandwidth. Comprehensive test scenarios are created using measurement data obtained from HW platforms, which are used to test and evaluate the performance of the developed interleaving mismatch estimation and correction schemes, evidencing excellent performance in all studied scenarios. The findings and results presented in this thesis contribute towards increasing the analog BW and conversion rate of ADC systems without losing conversion accuracy. Overall, these developments pave the way towards fulfilling the ever growing demands on the ADCs in terms of higher conversion BW, accuracy and speed

Modeling and Design of Architectures for High-Speed ADC-Based Serial Links

There is an ongoing dramatic rise in the volume of internet traffic. Standards such as 56Gb/s OIF very short reach (VSR), medium reach (MR) and long reach (LR) standards for chip to chip communication over channels with up to 10dB, 20dB and 30dB insertion loss at the PAM 4 Nyquist frequency, respectively, are being adopted. These standards call for the spectrally efficient PAM-4 signaling over NRZ signaling. PAM-4 signaling offers challenges such as a reduced SNR at the receiver, susceptibility to nonlinearities and increased sensitivity to residual ISI. Equalization provided by traditional mixed signal architectures can be insufficient to achieve the target BER requirements for very long reach channels. ADC-based receiver architectures for PAM-4 links take advantage of the more powerful equalization techniques, which lend themselves to easier and robust digital implementations, to extend the amount of insertion loss that the receiver can handle. However, ADC-based receivers can consume more power compared to mixed-signal implementations. Techniques that model the receiver performance to understand the various system trade-offs are necessary. This research presents a fast and accurate hybrid modeling framework to efficiently investigate system trade-offs for an ADC-based receiver. The key contribution being the addition of ADC related non-idealities such as quantization noise in the presence of integral and differential nonlinearities, and time-interleaving mismatch errors such as gain mismatch, bandwidth mismatch, offset mismatch and sampling skew. The research also presents a 52Gb/s ADC-based PAM-4 receiver prototype employing a 32-way time-interleaved, 2-bit/stage, 6-bit SAR ADC and a DSP with a 12-tap FFE and a 2-tap DFE. A new DFE architecture that reduces the complexity of a PAM-4 DFE to that of an NRZ DFE while simultaneously nearly doubling the maximum achievable data rate is presented. The receiver architecture also includes an analog front-end (AFE) consisting of a programmable two stage CTLE. A digital baud-rate CDR’s utilizing a Mueller-Muller phase detector sets the sampling phase. Measurement results show that for 32Gb/s operation a BER < 10⁻⁹ is achieved for a 30dB loss channel while for 52 Gb/s operation achieves a BER < 10⁻⁶ for a 31dB loss channel with a power efficiency of 8.06pj/bit

Energy-efficient analog-to-digital conversion for ultra-wideband radio

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 207-222).In energy constrained signal processing and communication systems, a focus on the analog or digital circuits in isolation cannot achieve the minimum power consumption. Furthermore, in advanced technologies with significant variation, yield is traditionally achieved only through conservative design and a sacrifice of energy efficiency. In this thesis, these limitations are addressed with both a comprehensive mixed-signal design methodology and new circuits and architectures, as presented in the context of an analog-to-digital converter (ADC) for ultra-wideband (UWB) radio. UWB is an emerging technology capable of high-data-rate wireless communication and precise locationing, and it requires high-speed (>500MS/s), low-resolution ADCs. The successive approximation register (SAR) topology exhibits significantly reduced complexity compared to the traditional flash architecture. Three time-interleaved SAR ADCs have been implemented. At the mixed-signal optimum energy point, parallelism and reduced voltage supplies provide more than 3x energy savings. Custom control logic, a new capacitive DAC, and a hierarchical sampling network enable the high-speed operation. Finally, only a small amount of redundancy, with negligible power penalty, dramatically improves the yield of the highly parallel ADC in deep sub-micron CMOS.by Brian P. Ginsburg.Ph.D