A Self-Sensing Method for Electromagnetic Actuators with Hysteresis Compensation

Self-Sensing techniques are a commonly used approach for electromagnetic actuators since they allow the removal of position sensors. Thus, costs, space requirements, and system complexity of actuation systems can be reduced. A widely used parameter for self-sensing is the position-dependent incremental inductance. Nevertheless, this parameter is strongly affected by electromagnetic hysteresis, which reduces the performance of self-sensing. This work focuses on the design of a hysteresis-compensated self-sensing algorithm with low computational effort. In particular, the Integrator-Based Direct Inductance Measurement (IDIM) technique is used for the resource-efficient estimation of the incremental inductance. Since the incremental inductance exhibits a hysteresis with butterfly characteristics, it first needs to be transformed into a B-H curve-like hysteresis. Then, a modified Prandtl–Ishlinskii (MPI) approach is used for modeling this hysteretic behavior. By using a lumped magnetic circuit model, the hysteresis of the iron core can be separated from the air gap, thus allowing a hysteresis-compensated estimation of the position. Experimental studies performed on an industrial switching actuator show a significant decrease in the estimation error when the hysteresis model is considered. The chosen MPI model has a low model order and therefore allows a computationally lightweight implementation. Therefore, it is proven that the presented approach increases the accuracy of self-sensing on electromagnetic actuators with remarkable hysteresis while offering low computational effort which is an important aspect for the implementation of the technique in cost-critical applications

Teaching Memory Circuit Elements via Experiment-Based Learning

The class of memory circuit elements which comprises memristive, memcapacitive, and meminductive systems, is gaining considerable attention in a broad range of disciplines. This is due to the enormous flexibility these elements provide in solving diverse problems in analog/neuromorphic and digital/quantum computation; the possibility to use them in an integrated computing-memory paradigm, massively-parallel solution of different optimization problems, learning, neural networks, etc. The time is therefore ripe to introduce these elements to the next generation of physicists and engineers with appropriate teaching tools that can be easily implemented in undergraduate teaching laboratories. In this paper, we suggest the use of easy-to-build emulators to provide a hands-on experience for the students to learn the fundamental properties and realize several applications of these memelements. We provide explicit examples of problems that could be tackled with these emulators that range in difficulty from the demonstration of the basic properties of memristive, memcapacitive, and meminductive systems to logic/computation and cross-bar memory. The emulators can be built from off-the-shelf components, with a total cost of a few tens of dollars, thus providing a relatively inexpensive platform for the implementation of these exercises in the classroom. We anticipate that this experiment-based learning can be easily adopted and expanded by the instructors with many more case studies.Comment: IEEE Circuits and Systems Magazine (in press

Memristors for the Curious Outsiders

We present both an overview and a perspective of recent experimental advances and proposed new approaches to performing computation using memristors. A memristor is a 2-terminal passive component with a dynamic resistance depending on an internal parameter. We provide an brief historical introduction, as well as an overview over the physical mechanism that lead to memristive behavior. This review is meant to guide nonpractitioners in the field of memristive circuits and their connection to machine learning and neural computation.Comment: Perpective paper for MDPI Technologies; 43 page

Neural-network dedicated processor for solving competitive assignment problems

A neural-network processor for solving first-order competitive assignment problems consists of a matrix of N x M processing units, each of which corresponds to the pairing of a first number of elements of (R sub i) with a second number of elements (C sub j), wherein limits of the first number are programmed in row control superneurons, and limits of the second number are programmed in column superneurons as MIN and MAX values. The cost (weight) W sub ij of the pairings is programmed separately into each PU. For each row and column of PU's, a dedicated constraint superneuron insures that the number of active neurons within the associated row or column fall within a specified range. Annealing is provided by gradually increasing the PU gain for each row and column or increasing positive feedback to each PU, the latter being effective to increase hysteresis of each PU or by combining both of these techniques

Everything You Wish to Know About Memristors But Are Afraid to Ask

This paper classifies all memristors into three classes called Ideal, Generic, or Extended memristors. A subclass of Generic memristors is related to Ideal memristors via a one-to-one mathematical transformation, and is hence called Ideal Generic memristors. The concept of non-volatile memories is defined and clarified with illustrations. Several fundamental new concepts, including Continuum-memory memristor, POP (acronym for Power-Off Plot), DC V-I Plot, and Quasi DC V-I Plot, are rigorously defined and clarified with colorful illustrations. Among many colorful pictures the shoelace DC V-I Plot stands out as both stunning and illustrative. Even more impressive is that this bizarre shoelace plot has an exact analytical representation via 2 explicit functions of the state variable, derived by a novel parametric approach invented by the author