Low power CMOS analog multipliers.

CMOS analog multiplier is a very important building block and programming element in analog signal processing. Although high-performance multipliers using bipolar transistors have been available for 40 years, CMOS multiplier implementation is still a challenging subject especially for low-power and low-noise circuit design. Since the supply voltage is normally fixed for analog multiplier structures, we use the total current to represent the power dissipation. Our basic idea for low power design of analog multipliers is to fit most of the transistors into the linear region, while at the same time keeping the drain-to-source voltage as low as possible to decease the drain current. And also, we use PMOS transistors for the devices working in the saturation region to further decrease the drain current and improve the linearity performance. Two low power CMOS analog multiplier designs have been proposed in this thesis. We gave detailed performance analysis and some design considerations for these structures. Cadence Hspice simulation verified our analysis. To ensure a fair comparison, we also simulated the performance of a previous multiplier structure, which was considered to be one of the best multiplier structures with low power and low noise performance. Extensive experiments and comparison for these structures show that the proposed CMOS analog multipliers have much less power dissipation than that of previous structures, while at the same time, satisfying other performance requirements. The proposed analog multipliers would be good choices in the applications where low power dissipation is an important consideration.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .L5. Source: Masters Abstracts International, Volume: 43-01, page: 0280. Adviser: Chunhong Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Low Power CMOS Analog Multiplier

Abstract In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it consumes only 31.8µW quiescent power and 110MHZ bandwidth

130 nm low power CMOS analog multiplier

Processing analog signal often involves analog multiplier and the multiplier is part of system on chip (SoC). Designing such system with a low power consumption is crucial nowadays. It is very important to increase the system battery lifetime. The design also must be smaller in size. In order to reduce the power consumption of the multiplier, an architecture that require smaller current must be designed and the approach is to use a design that is able to function at a low voltage supply. This project has designed the analog multiplier with a low power consumption using Silterra 130 nm Complementary Metal Oxide Semiconductor (CMOS) technology. A four quadrant technique is applied in the design. The scaling of transistor will help in reducing the size of the analog multiplier, and the proposed circuit architecture has produced a compact multiplier. Cadence electronic design automation (EDA) Tools is used to design the circuit. The schematic, layout, physical verification and parasitic extraction with post layout simulation are done to verify the multiplier circuit is functioning. The analog multiplier is operated with 1.2 V voltage supply and the power consumption is 98 μW. At 1 V, the power consumption is 32 μW. The total area for the design is 99 μm²

A Design of Analog Voltage-Mode Multiplier for UHF RFID in 0.18um CMOS process

In this paper a “Low Voltage, Low Power, High Speed and High Linearity-CMOS Analog Multiplier for Modem ASK is proposed”. The multiplier circuit is implemented in 180nm CMOS technology. It can be operated even at low Supply voltage VDD=0.9V. Band width of operation is about 4.10MHz, which is suitable for high frequency/high speed applications. This device modulates an analog carrier signal to encode digital information, and also demodulates such a carrier signal to decode the transmitted information. The goal is to produce a signal that can be transmitted easily and decoded to reproduce the original digital data

ASIC Design to Support Low Power High Voltage Power Supply for Radiation Monitoring Applications

A low power high voltage power supply is designed for use in a long duration radiation monitoring system. The supply employs a flexible pulse frequency modulation switching controller implemented in a 0.35 $\mu$m CMOS technology. The controller drives and regulates a flyback transformer driven 12-stage Cockroft-Walton voltage multiplier chain. The chain provides bias for the dynodes of a photomultiplier tube. The supply voltage is selectable via a 12-bit on-chip digital to analog converter. The system is designed for low power operation and immunity to supply voltage variation as the application is battery-powered. Advisors: Sina Balkir and Michael Hoffma

CMOS design of a current-mode multiplier/divider circuit with applications to fuzzy controllers

Multiplier and divider circuits are usually required in the fields of analog signal processing and parallel-computing neural or fuzzy systems. In particular, this paper focuses on the hardware implementation of fuzzy controllers, where the divider circuit is usually the bottleneck. Multiplier/divider circuits can be implemented with a combination of A/D-D/A converters. An efficient design based on current-mode data converters is presented herein. Continuous-time algorithmic converters are chosen to reduce the control circuitry and to obtain a modular design based on a cascade of bit cells. Several circuit structures to implement these cells are presented and discussed. The one that is selected enables a better trade-off speed/power than others previously reported in the literature while maintaining a low area occupation. The resulting multiplier/divider circuit offers a low voltage operation, provides the division result in both analog and digital formats, and it is suitable for applications of low or middle resolution (up to 9 bits) like applications to fuzzy controllers. The analysis is illustrated with Hspice simulations and experimental results from a CMOS multiplier/divider prototype with 5-bit resolution. Experimental results from a CMOS current-mode fuzzy controller chip that contains the proposed design are also included

Low Voltage Floating Gate MOS Transistor Based Four-Quadrant Multiplier

This paper presents a four-quadrant multiplier based on square-law characteristic of floating gate MOSFET (FGMOS) in saturation region. The proposed circuit uses square-difference identity and the differential voltage squarer proposed by Gupta et al. to implement the multiplication function. The proposed multiplier employs eight FGMOS transistors and two resistors only. The FGMOS implementation of the multiplier allows low voltage operation, reduced power consumption and minimum transistor count. The second order effects caused due to mobility degradation, component mismatch and temperature variations are discussed. Performance of the proposed circuit is verified at ±0.75 V in TSMC 0.18 µm CMOS, BSIM3 and Level 49 technology by using Cadence Spectre simulator

A wideband linear tunable CDTA and its application in field programmable analogue array

This document is the Accepted Manuscript version of the following article: Hu, Z., Wang, C., Sun, J. et al. ‘A wideband linear tunable CDTA and its application in field programmable analogue array’, Analog Integrated Circuits and Signal Processing, Vol. 88 (3): 465-483, September 2016. Under embargo. Embargo end date: 6 June 2017. The final publication is available at Springer via https://link.springer.com/article/10.1007%2Fs10470-016-0772-7 © Springer Science+Business Media New York 2016In this paper, a NMOS-based wideband low power and linear tunable transconductance current differencing transconductance amplifier (CDTA) is presented. Based on the NMOS CDTA, a novel simple and easily reconfigurable configurable analogue block (CAB) is designed. Moreover, using the novel CAB, a simple and versatile butterfly-shaped FPAA structure is introduced. The FPAA consists of six identical CABs, and it could realize six order current-mode low pass filter, second order current-mode universal filter, current-mode quadrature oscillator, current-mode multi-phase oscillator and current-mode multiplier for analog signal processing. The Cadence IC Design Tools 5.1.41 post-layout simulation and measurement results are included to confirm the theory.Peer reviewedFinal Accepted Versio