363 research outputs found

    Design of CMOS UWB LNA

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    A New CMOS Fully Differential Low Noise Amplifier for Wideband Applications

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    In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for wideband applications. A common-gate input stage is used to improve the input impedance matching and linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure (NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply voltage of 0.8v

    Current reuse topology in UWB CMOS LNA

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    Mixed Linearity Improvement Techniques for Ultra-wideband Low Noise Amplifier

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    We present the linearization of an ultra-wideband low noise amplifier (UWB-LNA) operating from 2GHz to 11GHz through combining two linearization methods. The used linearization techniques are the combination of post-distortion cancellation and derivative-superposition linearization methods. The linearized UWB-LNA shows an improved linearity (IIP3) of +12dBm, a minimum noise figure (NFmin.) of 3.6dB, input and output insertion losses (S11 and S22)  below -9dB over the entire working bandwidth, midband gain of 6dB at 5.8GHz, and overall circuit power consumption of 24mW supplied from a 1.5V voltage source. Both UWB-LNA and linearized UWB-LNA designs are verified and simulated with ADS2016.01 software using BSIM3v3 TSMC 180nm CMOS model files. In addition, the linearized UWB-LNA performance is compared with other recent state-of-the-art LNAs

    LNA for UWB transceiver using 0.18µm CMOS Technology

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    An Ultra WideBand CMOS Low Noise Amplifier (LNA) is presented. Due to really low power consumption and extremely high data rates the UWB standard is bound to be popular in the consumer market. The LNA is the outer most part of an UWB transceiver. The LNA is responsible for providing enough gain to the signal with the least distortion possible. CMOS 0.18µm TSMC technology has been chosen for the design of the LNA at the transistor level. As many as five on chip inductors are implemented for the proper gain shaping over the frequency range of 3.1GHz to 10.6GHz. A noise figure of 3.98 dB is achieved to make sure noise contribution of the amplifier is as low as possible

    High frequency of low noise amplifier architecture for WiMAX application: A review

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    The low noise amplifier (LNA) circuit is exceptionally imperative as it promotes and initializes general execution performance and quality of the mobile communication system. LNA's design in radio frequency (R.F.) circuit requires the trade-off numerous imperative features' including gain, noise figure (N.F.), bandwidth, stability, sensitivity, power consumption, and complexity. Improvements to the LNA's overall performance should be made to fulfil the worldwide interoperability for microwave access (WiMAX) specifications' prerequisites. The development of front-end receiver, particularly the LNA, is genuinely pivotal for long-distance communications up to 50 km for a particular system with particular requirements. The LNA architecture has recently been designed to concentrate on a single transistor, cascode, or cascade constrained in gain, bandwidth, and noise figure

    A Novel High Linearity and Low Power Folded CMOS LNA for UWB Receivers

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    © 2017 World Scientific Publishing Company. Electronic version of an article published as Journal of Circuits, Systems and Computers, Vol. 27, No. 03, 1850047, https://doi.org/10.1142/S0218126618500470.This paper presents a high linearity and low power Low-Noise Amplifier (LNA) for Ultra-Wideband (UWB) receivers based on CHRT 0.18μm CMOS technology. In this work, the folded topology is adopted in order to reduce the supply voltage and power consumption. Moreover, a band-pass LC filter is embedded in the folded-cascode circuit to extend bandwidth. The transconductance nonlinearity has a great impact on the whole LNA linearity performance under a low supply voltage. A post-distortion (PD) technique employing an auxiliary transistor is applied in the transconductance stage to improve the linearity. The post-layout simulation results indicate that the proposed LNA achieves a maximum power gain of 12.8dB. The input and output reflection coefficients both are lower than -10.0dB over 2.5~11.5GHz. The input third-order intercept point (IIP3) is 5.6dBm at 8GHz and the noise figure (NF) is lower than 4.0dB. The LNA consumes 5.4mW power under a 1V supply voltage.Peer reviewe
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