A 0.1–5.0 GHz flexible SDR receiver with digitally assisted calibration in 65 nm CMOS

© 2017 Elsevier Ltd. All rights reserved.A 0.1–5.0 GHz flexible software-defined radio (SDR) receiver with digitally assisted calibration is presented, employing a zero-IF/low-IF reconfigurable architecture for both wideband and narrowband applications. The receiver composes of a main-path based on a current-mode mixer for low noise, a high linearity sub-path based on a voltage-mode passive mixer for out-of-band rejection, and a harmonic rejection (HR) path with vector gain calibration. A dual feedback LNA with “8” shape nested inductor structure, a cascode inverter-based TCA with miller feedback compensation, and a class-AB full differential Op-Amp with Miller feed-forward compensation and QFG technique are proposed. Digitally assisted calibration methods for HR, IIP2 and image rejection (IR) are presented to maintain high performance over PVT variations. The presented receiver is implemented in 65 nm CMOS with 5.4 mm2 core area, consuming 9.6–47.4 mA current under 1.2 V supply. The receiver main path is measured with +5 dB m/+5dBm IB-IIP3/OB-IIP3 and +61dBm IIP2. The sub-path achieves +10 dB m/+18dBm IB-IIP3/OB-IIP3 and +62dBm IIP2, as well as 10 dB RF filtering rejection at 10 MHz offset. The HR-path reaches +13 dB m/+14dBm IB-IIP3/OB-IIP3 and 62/66 dB 3rd/5th-order harmonic rejection with 30–40 dB improvement by the calibration. The measured sensitivity satisfies the requirements of DVB-H, LTE, 802.11 g, and ZigBee.Peer reviewedFinal Accepted Versio

A Fully-Integrated Reconfigurable Dual-Band Transceiver for Short Range Wireless Communications in 180 nm CMOS

© 2015 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.A fully-integrated reconfigurable dual-band (760-960 MHz and 2.4-2.5 GHz) transceiver (TRX) for short range wireless communications is presented. The TRX consists of two individually-optimized RF front-ends for each band and one shared power-scalable analog baseband. The sub-GHz receiver has achieved the maximum 75 dBc 3rd-order harmonic rejection ratio (HRR3) by inserting a Q-enhanced notch filtering RF amplifier (RFA). In 2.4 GHz band, a single-ended-to-differential RFA with gain/phase imbalance compensation is proposed in the receiver. A ΣΔ fractional-N PLL frequency synthesizer with two switchable Class-C VCOs is employed to provide the LOs. Moreover, the integrated multi-mode PAs achieve the output P1dB (OP1dB) of 16.3 dBm and 14.1 dBm with both 25% PAE for sub-GHz and 2.4 GHz bands, respectively. A power-control loop is proposed to detect the input signal PAPR in real-time and flexibly reconfigure the PA's operation modes to enhance the back-off efficiency. With this proposed technique, the PAE of the sub-GHz PA is improved by x3.24 and x1.41 at 9 dB and 3 dB back-off powers, respectively, and the PAE of the 2.4 GHz PA is improved by x2.17 at 6 dB back-off power. The presented transceiver has achieved comparable or even better performance in terms of noise figure, HRR, OP1dB and power efficiency compared with the state-of-the-art.Peer reviewe

Low-Noise Micro-Power Amplifiers for Biosignal Acquisition

There are many different types of biopotential signals, such as action potentials (APs), local field potentials (LFPs), electromyography (EMG), electrocardiogram (ECG), electroencephalogram (EEG), etc. Nerve action potentials play an important role for the analysis of human cognition, such as perception, memory, language, emotions, and motor control. EMGs provide vital information about the patients which allow clinicians to diagnose and treat many neuromuscular diseases, which could result in muscle paralysis, motor problems, etc. EEGs is critical in diagnosing epilepsy, sleep disorders, as well as brain tumors. Biopotential signals are very weak, which requires the biopotential amplifier to exhibit low input-referred noise. For example, EEGs have amplitudes from 1 μV [microvolt] to 100 μV [microvolt] with much of the energy in the sub-Hz [hertz] to 100 Hz [hertz] band. APs have amplitudes up to 500 μV [microvolt] with much of the energy in the 100 Hz [hertz] to 7 kHz [hertz] band. In wearable/implantable systems, the low-power operation of the biopotential amplifier is critical to avoid thermal damage to surrounding tissues, preserve long battery life, and enable wirelessly-delivered or harvested energy supply. For an ideal thermal-noise-limited amplifier, the amplifier power is inversely proportional to the input-referred noise of the amplifier. Therefore, there is a noise-power trade-off which must be well-balanced by the designers. In this work I propose novel amplifier topologies, which are able to significantly improve the noise-power efficiency by increasing the effective transconductance at a given current. In order to reject the DC offsets generated at the tissue-electrode interface, energy-efficient techniques are employed to create a low-frequency high-pass cutoff. The noise contribution of the high-pass cutoff circuitry is minimized by using power-efficient configurations, and optimizing the biasing and dimension of the devices. Sufficient common-mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) are achieved to suppress common-mode interferences and power supply noises. Our design are fabricated in standard CMOS processes. The amplifiers’ performance are measured on the bench, and also demonstrated with biopotential recordings

Recursive receiver down-converters with multiband feedback and gain-reuse for low-power applications

Power minimization in wireless transceivers has become increasingly critical in recent years with the emergence of standards for short-distance applications in the 900 MHz and 2.4 GHz industrial, scientific and medical (ISM) radio bands. The demand for long battery life and better portability in such applications has led to extensive research on low power radio architectures. This dissertation introduces receiver topologies for low-power systems and presents a theoretical performance analysis of the topologies. Two fully integrated receiver down-converters that demonstrate the concept are implemented in a 0.13-[mu]m CMOS technology. These topologies employ merged mixers and IF amplifiers in order to reduce power dissipation for a given dynamic range performance. In the described topologies, the input stage of a mixer is used to simultaneously provide conversion gain and baseband amplification. This is achieved by applying the down-converted IF signal to input of the mixer. Consequently, the effective conversion gain of the design is greatly enhanced with current requirement primarily determined by the input transconductor. Potential degradation mechanisms related to instability and second-order distortion are identified and solved by the use of appropriate circuit techniques. Noise and linearity performance of the down-converters is analyzed and compared to that of conventional cascaded design counterparts. The potential for enhancement of IIP3 performance through cancellation of nonlinear products is discussed. Potential extensions of the above work including feedback-based architectures that exploit multiple loops for further maximizing the power efficiency of receiver front-ends are also presented.Electrical and Computer Engineerin

A New CMOS Fully Differential Low Noise Amplifier for Wideband Applications

In this paper, a multi-stage fully differential low noise amplifier (LNA) has been presented for wideband applications. A common-gate input stage is used to improve the input impedance matching and linearity. A common-source stage is also used as the second stage to enhance gain and reduce noise. A shunt-shunt feedback is employed to extend bandwidth and enhance linearity. The proposed low noise amplifier has been designed and simulated using RF-TSMC 0.18 μm CMOS process technology. In frequency band of 3.5-7.5 GHz, this amplifier has a flat power gain (S21) of 16.5 ± 1.5 dB, low noise figure (NF) of 3dB, input (S11) and output (S22) return losses less than -10 dB and high linearity with input thirdorder intercept point (IIP3) of -3dBm. It’s power consumption is also less than 10 mw with low power supply voltage of 0.8v

Reconfigurable Receiver Front-Ends for Advanced Telecommunication Technologies

The exponential growth of converging technologies, including augmented reality, autonomous vehicles, machine-to-machine and machine-to-human interactions, biomedical and environmental sensory systems, and artificial intelligence, is driving the need for robust infrastructural systems capable of handling vast data volumes between end users and service providers. This demand has prompted a significant evolution in wireless communication, with 5G and subsequent generations requiring exponentially improved spectral and energy efficiency compared to their predecessors. Achieving this entails intricate strategies such as advanced digital modulations, broader channel bandwidths, complex spectrum sharing, and carrier aggregation scenarios. A particularly challenging aspect arises in the form of non-contiguous aggregation of up to six carrier components across the frequency range 1 (FR1). This necessitates receiver front-ends to effectively reject out-of-band (OOB) interferences while maintaining high-performance in-band (IB) operation. Reconfigurability becomes pivotal in such dynamic environments, where frequency resource allocation, signal strength, and interference levels continuously change. Software-defined radios (SDRs) and cognitive radios (CRs) emerge as solutions, with direct RF-sampling receivers offering a suitable architecture in which the frequency translation is entirely performed in digital domain to avoid analog mixing issues. Moreover, direct RF- sampling receivers facilitate spectrum observation, which is crucial to identify free zones, and detect interferences. Acoustic and distributed filters offer impressive dynamic range and sharp roll off characteristics, but their bulkiness and lack of electronic adjustment capabilities limit their practicality. Active filters, on the other hand, present opportunities for integration in advanced CMOS technology, addressing size constraints and providing versatile programmability. However, concerns about power consumption, noise generation, and linearity in active filters require careful consideration.This thesis primarily focuses on the design and implementation of a low-voltage, low-power RFFE tailored for direct sampling receivers in 5G FR1 applications. The RFFE consists of a balun low-noise amplifier (LNA), a Q-enhanced filter, and a programmable gain amplifier (PGA). The balun-LNA employs noise cancellation, current reuse, and gm boosting for wideband gain and input impedance matching. Leveraging FD-SOI technology allows for programmable gain and linearity via body biasing. The LNA's operational state ranges between high-performance and high-tolerance modes, which are apt for sensitivityand blocking tests, respectively. The Q-enhanced filter adopts noise-cancelling, current-reuse, and programmable Gm-cells to realize a fourth-order response using two resonators. The fourth-order filter response is achieved by subtracting the individual response of these resonators. Compared to cascaded and magnetically coupled fourth-order filters, this technique maintains the large dynamic range of second-order resonators. Fabricated in 22-nm FD-SOI technology, the RFFE achieves 1%-40% fractional bandwidth (FBW) adjustability from 1.7 GHz to 6.4 GHz, 4.6 dB noise figure (NF) and an OOB third-order intermodulation intercept point (IIP3) of 22 dBm. Furthermore, concerning the implementation uncertainties and potential variations of temperature and supply voltage, design margins have been considered and a hybrid calibration scheme is introduced. A combination of on-chip and off-chip calibration based on noise response is employed to effectively adjust the quality factors, Gm-cells, and resonance frequencies, ensuring desired bandpass response. To optimize and accelerate the calibration process, a reinforcement learning (RL) agent is used.Anticipating future trends, the concept of the Q-enhanced filter extends to a multiple-mode filter for 6G upper mid-band applications. Covering the frequency range from 8 to 20 GHz, this RFFE can be configured as a fourth-order dual-band filter, two bandpass filters (BPFs) with an OOB notch, or a BPF with an IB notch. In cognitive radios, the filter’s transmission zeros can be positioned with respect to the carrier frequencies of interfering signals to yield over 50 dB blocker rejection

Advances in Microelectronics for Implantable Medical Devices

Implantable medical devices provide therapy to treat numerous health conditions as well as monitoring and diagnosis. Over the years, the development of these devices has seen remarkable progress thanks to tremendous advances in microelectronics, electrode technology, packaging and signal processing techniques. Many of today’s implantable devices use wireless technology to supply power and provide communication. There are many challenges when creating an implantable device. Issues such as reliable and fast bidirectional data communication, efficient power delivery to the implantable circuits, low noise and low power for the recording part of the system, and delivery of safe stimulation to avoid tissue and electrode damage are some of the challenges faced by the microelectronics circuit designer. This paper provides a review of advances in microelectronics over the last decade or so for implantable medical devices and systems. The focus is on neural recording and stimulation circuits suitable for fabrication in modern silicon process technologies and biotelemetry methods for power and data transfer, with particular emphasis on methods employing radio frequency inductive coupling. The paper concludes by highlighting some of the issues that will drive future research in the field

CURRENT REUSE ACTIVE INDUCTOR BASED WIDEBAND LNA

This paper presents the design of an active inductor based wideband LNA using current reuse topology,which is designed and simulated in 0.18um CMOS technology. The low noise amplifier is considered to be the key block in an RF receiver. It plays a critical role in determining the noise figure of a receiver. The main function of an LNA is to provide sufficient gain to reduce the noise of subsequent stages while adding as little noise as possible. To achieve a good impedance matching over a desire bandwidth (0.05GHz to1.5GHz) active inductor is implemented based on gyrator structure and its noise is improved by employing a feed-forward path (FFP). The simulations show a maximum power gain of 17.32dB, minimum noise figure (NF) of 0.87dB with a 3db bandwidth of 1.0GHz over 0.05-1.5 GHz range. The total power consumption is 6.38mW with 1.8V power supply

Design and Simulation of Two Stage Wideband CMOS Amplifier in 90 NM Technology

Design and simulation of 7 GHz CMOS wideband amplifier(CMOSWA) using a modified cascode circuit realized in  90-nm CMOS technology is presented here. The proposed system consists of two stages, namely a modified folded cascode and an inductively degenerated common source amplifier. The circuit is experimented with and without a feedback network. This work discusses the performance variation as a function of reactive components, and the initial stage results in 22 dB gain,2.6 GHz bandwidth, and 40GHz unity gain-bandwidth. The circuit without the feedback network exhibits 30.7dB gain,4.8GHz bandwidth(BW), and 10GHz unity-gain bandwidth(UGB). The reactive feedback network's inclusion helped to achieve 38.7 dB gain, 6.95GHz BW, 30GHz UGB, and 55o phase margin. The circuit consumes 1.4mW power from a 1.8V power supply. Simulation results of the proposed circuit are comparable and better than the reported wideband designs in the literature. Realization of our proposed circuit would add value to the area of wideband amplifier design

Survey on individual components for a 5 GHz receiver system using 130 nm CMOS technology

La intención de esta tesis es recopilar información desde un punto de vista general sobre los diferentes tipos de componentes utilizados en un receptor de señales a 5 GHz utilizando tecnología CMOS. Se ha realizado una descripción y análisis de cada uno de los componentes que forman el sistema, destacando diferentes tipos de configuraciones, figuras de mérito y otros parámetros. Se muestra una tabla resumen al final de cada sección, comparando algunos diseños que se han ido presentando a lo largo de los años en conferencias internacionales de la IEEE.The intention of this thesis is to gather information from an overview point about the different types of components used in a 5 GHz receiver using CMOS technology. A review of each of the components that form the system has been made, highlighting different types of configurations, figure of merits and parameters. A summary table is shown at the end of each section, comparing many designs that have been presented over the years at international conferences of the IEEE.Departamento de Ingeniería Energética y FluidomecánicaGrado en Ingeniería en Electrónica Industrial y Automátic