165 research outputs found
Ultra-low noise, high-frame rate readout design for a 3D-stacked CMOS image sensor
Due to the switch from CCD to CMOS technology, CMOS based image sensors have become
smaller, cheaper, faster, and have recently outclassed CCDs in terms of image quality. Apart
from the extensive set of applications requiring image sensors, the next technological
breakthrough in imaging would be to consolidate and completely shift the conventional CMOS
image sensor technology to the 3D-stacked technology. Stacking is recent and an innovative
technology in the imaging field, allowing multiple silicon tiers with different functions to be
stacked on top of each other. The technology allows for an extreme parallelism of the pixel
readout circuitry. Furthermore, the readout is placed underneath the pixel array on a 3D-stacked
image sensor, and the parallelism of the readout can remain constant at any spatial resolution of
the sensors, allowing extreme low noise and a high-frame rate (design) at virtually any sensor
array resolution.
The objective of this work is the design of ultra-low noise readout circuits meant for 3D-stacked
image sensors, structured with parallel readout circuitries. The readout circuitâs key
requirements are low noise, speed, low-area (for higher parallelism), and low power.
A CMOS imaging review is presented through a short historical background, followed by the
description of the motivation, the research goals, and the work contributions. The fundamentals
of CMOS image sensors are addressed, as a part of highlighting the typical image sensor features,
the essential building blocks, types of operation, as well as their physical characteristics and their
evaluation metrics. Following up on this, the document pays attention to the readout circuitâs
noise theory and the column converters theory, to identify possible pitfalls to obtain sub-electron
noise imagers. Lastly, the fabricated test CIS device performances are reported along with
conjectures and conclusions, ending this thesis with the 3D-stacked subject issues and the future
work. A part of the developed research work is located in the Appendices.Devido à mudança da tecnologia CCD para CMOS, os sensores de imagem em CMOS tornam se mais pequenos, mais baratos, mais råpidos, e mais recentemente, ultrapassaram os sensores
CCD no que respeita à qualidade de imagem. Para além do vasto conjunto de aplicaçÔes que
requerem sensores de imagem, o prĂłximo salto tecnolĂłgico no ramo dos sensores de imagem Ă©
o de mudar completamente da tecnologia de sensores de imagem CMOS convencional para a
tecnologia â3D-stackedâ. O empilhamento de chips Ă© relativamente recente e Ă© uma tecnologia
inovadora no campo dos sensores de imagem, permitindo vĂĄrios planos de silĂcio com diferentes
funçÔes poderem ser empilhados uns sobre os outros. Esta tecnologia permite portanto, um
paralelismo extremo na leitura dos sinais vindos da matriz de pĂxeis. AlĂ©m disso, num sensor de
imagem de planos de silĂcio empilhados, os circuitos de leitura estĂŁo posicionados debaixo da
matriz de pĂxeis, sendo que dessa forma, o paralelismo pode manter-se constante para qualquer
resolução espacial, permitindo assim atingir um extremo baixo ruĂdo e um alto debito de
imagens, virtualmente para qualquer resolução desejada.
O objetivo deste trabalho Ă© o de desenhar circuitos de leitura de coluna de muito baixo ruĂdo,
planeados para serem empregues em sensores de imagem â3D-stackedâ com estruturas
altamente paralelizadas. Os requisitos chave para os circuitos de leitura sĂŁo de baixo ruĂdo,
rapidez e pouca ĂĄrea utilizada, de forma a obter-se o melhor rĂĄcio.
Uma breve revisĂŁo histĂłrica dos sensores de imagem CMOS Ă© apresentada, seguida da
motivação, dos objetivos e das contribuiçÔes feitas. Os fundamentos dos sensores de imagem
CMOS sĂŁo tambĂ©m abordados para expor as suas caracterĂsticas, os blocos essenciais, os tipos
de operação, assim como as suas caracterĂsticas fĂsicas e suas mĂ©tricas de avaliação. No
seguimento disto, especial atenção Ă© dada Ă teoria subjacente ao ruĂdo inerente dos circuitos de
leitura e dos conversores de coluna, servindo para identificar os possĂveis aspetos que dificultem
atingir a tĂŁo desejada performance de muito baixo ruĂdo. Por fim, os resultados experimentais
do sensor desenvolvido sĂŁo apresentados junto com possĂveis conjeturas e respetivas conclusĂ”es,
terminando o documento com o assunto de empilhamento vertical de camadas de silĂcio, junto
com o possĂvel trabalho futuro
Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier
An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures
Pulse frequency modulated DROICs with reduced quantization noise employing extended counting method
Reducing the system size and weight is a very competitive advantage in todayâs IR market. A continuously growing effort has been shown to achieve digital output ROICs over the last decade with a primary concern to reduce the overall imaging system size and power by eliminating off chip ADCs and precise analog buffers as well as reducing the size of periphery boards. There is an unnamed industry standard of 20mK NETD for military IR imaging applications. A lower value is always desired to improve image quality or for track and search systems higher correct decision probabilities. Photon noise is the primary noise source and follow shot noise behavior and ideal SNR is limited with the square root of the stored charges. The limiting issue for higher SNR is due the limited charge handling capacity in a small pixel area. Recent works have shown DROICs with very high charge handling capacities on the order of giga electrons and SNR values as high as 90dB. The drawbacks of these works are the high quantization noise which makes their use limited to high flux scenes or low frame rate applications and high power dissipation which limits the use to small or moderate size array dimensions. In order to overcome these issues, this thesis has proposed circuit architectures with quantization noise levels lower than 200 electrons with 22 bit representation for a charge handling capacity of 2.34Ge-. The architecture relies on PFM pixel followed by a novel per pixel residue measurement method. A 32x32 prototype array has been fabricated and tested for verification of the proposed architecture. Design considerations have been followed for 256x256 array with a high frame rate of 400Hz and power dissipation of 22.21mW and a peak SNR of 71dB. Additionally low power operation of the proposed DROIC architecture with respect to ordinary PFM DROICs has been analyzed
Low Power Analog to Digital Converters in Advanced CMOS Technology Nodes
The dissertation presents system and circuit solutions to improve the power efficiency and address high-speed design issues of ADCs in advanced CMOS technologies.
For image sensor applications, a high-performance digitizer prototype based on column-parallel single-slope ADC (SS-ADC) topology for readout of a back-illuminated 3D-stacked CMOS image sensor is presented. To address the high power consumption issue in high-speed digital counters, a passing window (PW) based hybrid counter topology is proposed. To address the high column FPN under bright illumination conditions, a double auto-zeroing (AZ) scheme is proposed. The proposed techniques are experimentally verified in a prototype chip designed and fabricated in the TSMC 40 nm low-power CMOS process. The PW technique saves 52.8% of power consumption in the hybrid digital counters. Dark/bright column fixed pattern noise (FPN) of 0.0024%/0.028% is achieved employing the proposed double AZ technique for digital correlated double sampling (CDS). A single-column digitizer consumes total power of 66.8ΌW and occupies an area of 5.4 ”m x 610 ”m.
For mobile/wireless receiver applications, this dissertation presents a low-power wide-bandwidth multistage noise-shaping (MASH) continuous-time delta-sigma modulator (CT-ÎÎŁM) employing finite impulse response (FIR) digital-to-analog converters (DACs) and encoder-embedded loop-unrolling (EELU) quantizers. The proposed MASH 1-1-1 topology is a cascade of three single-loop first-order CT-ÎÎŁM stages, each of which consists of an active-RC integrator, a current-steering DAC, and an EELU quantizer. An FIR filter in the main 1.5-bit DAC improves the modulatorâs jitter sensitivity performance. FIRâs effect on the noise transfer function (NTF) of the modulator is compensated in the digital domain thanks to the MASH topology. Instead of employing a conventional analog direct feedback path, a 1.5-bit EELU quantizer based on multiplexing comparator outputs is proposed; this approach is suitable for highspeed operation together with power and area benefits. Fabricated in a 40-nm low-power CMOS technology, the modulatorâs prototype achieves a 67.3 dB of signal-to-noise and distortion ratio (SNDR), 68 dB of signal-to-noise ratio (SNR), and 68.2 dB of dynamic range (DR) within 50.5 MHz of bandwidth (BW), while consuming 19 mW of total power (P). The proposed modulator features 161.5 dB of figure-of-merit (FOM), defined as FOM = SNDR + 10 log10 (BW/P)
Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters
Analog-to-digital converters (ADCs) are key design blocks in
state-of-art image, capacitive, and biomedical sensing applications.
In these sensing applications, algorithmic ADCs are the preferred
choice due to their high resolution and low area advantages.
Algorithmic ADCs are based on the same operating principle as that
of pipelined ADCs. Unlike pipelined ADCs where the residue is
transferred to the next stage, an N-bit algorithmic ADC utilizes the
same hardware N-times for each bit of resolution. Due to the
cyclic nature of algorithmic ADCs, many of the low power techniques
applicable to pipelined ADCs cannot be
directly applied to algorithmic ADCs. Consequently, compared to those of
pipelined ADCs, the traditional implementations of algorithmic ADCs are
power inefficient.
This thesis presents two novel energy efficient techniques for algorithmic
ADCs. The first technique modifies the capacitors' arrangement of a
conventional flip-around configuration and amplifier sharing
technique, resulting in a low power and low area design solution. The
other technique is based on the unit
multiplying-digital-to-analog-converter approach. The proposed
approach exploits the power saving advantages of capacitor-shared technique
and capacitor-scaled technique. It is shown that, compared to
conventional techniques, the proposed techniques reduce the
power consumption of algorithmic ADCs by more than 85\%.
To verify the effectiveness of such approaches, two
prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are
implemented in a 130-nm CMOS process. Detailed design considerations
are discussed as well as the simulation and measurement results. According to the
simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step,
making them some of the most power efficient ADCs to date
Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters
Analog-to-digital converters (ADCs) are key design blocks in
state-of-art image, capacitive, and biomedical sensing applications.
In these sensing applications, algorithmic ADCs are the preferred
choice due to their high resolution and low area advantages.
Algorithmic ADCs are based on the same operating principle as that
of pipelined ADCs. Unlike pipelined ADCs where the residue is
transferred to the next stage, an N-bit algorithmic ADC utilizes the
same hardware N-times for each bit of resolution. Due to the
cyclic nature of algorithmic ADCs, many of the low power techniques
applicable to pipelined ADCs cannot be
directly applied to algorithmic ADCs. Consequently, compared to those of
pipelined ADCs, the traditional implementations of algorithmic ADCs are
power inefficient.
This thesis presents two novel energy efficient techniques for algorithmic
ADCs. The first technique modifies the capacitors' arrangement of a
conventional flip-around configuration and amplifier sharing
technique, resulting in a low power and low area design solution. The
other technique is based on the unit
multiplying-digital-to-analog-converter approach. The proposed
approach exploits the power saving advantages of capacitor-shared technique
and capacitor-scaled technique. It is shown that, compared to
conventional techniques, the proposed techniques reduce the
power consumption of algorithmic ADCs by more than 85\%.
To verify the effectiveness of such approaches, two
prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are
implemented in a 130-nm CMOS process. Detailed design considerations
are discussed as well as the simulation and measurement results. According to the
simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step,
making them some of the most power efficient ADCs to date
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Fully-passive switched-capacitor techniques for high performance SAR ADC design
In recent years, SAR ADC becomes more and more popular in various low-power applications such as wireless sensors and low energy radios due to its circuit simplicity, high power efficiency, and scaling compatibility. However, its speed is limited by its successive approximation procedures and its power efficiency greatly reduces with the ADC resolution going beyond 10 bit. To address these issues, this thesis proposes to embed two techniques: 1) compressive sensing (CS) and 2) noise shaping (NS) to a conventional SAR ADC. The realization of both techniques are based on fully-passive switched-capacitor techniques.
CS is a recently emerging sampling paradigm, stating that the sparsity of a signal can be exploited to reduce the ADC sampling rate below the Nyquist rate. Different from conventional CS frameworks which require dedicated analog CS encoders, this thesis proposes a fully-passive CS-SAR ADC architecture which only requires minor modification to a conventional SAR ADC. Two chips are fabricated in a 0.13 ”m process to prove the concept. One chip is a single-channel CS-SAR ADC which can reduce the ADC conversion rate by 4 times, thus reducing the ADC power by 4 times. In many wireless sensing applications, multiple ADCs are commonly required to sense multi-channel signals such as multi-lead ECG sensing and parallel neural recording. Therefore, the other chip is a multi-channel CS-SAR ADC which can simultaneously convert 4-channel signals with a sampling rate of one channelâs Nyquist rate. At 0.8 V and 1 MS/s, both chips achieve an effective Walden FoM of around 5 fJ/conversion-step.
This thesis also proposes a novel NS SAR ADC architecture that is simple, robust and low power for high-resolution applications. Compared to conventional âÎŁ ADCs, it replaces the power-hungry active integrator with a passive integrator which only requires one switch and two capacitors. Compared to previous 1st-order NS SAR ADC works, it achieves the best NS performance and can be easily extended to 2nd-order. A 1st-order 10-bit NS SAR ADC is fabricated in a 0.13 ”m process. Through NS, SNDR increases by 6 dB with OSR doubled, achieving a 12- bit ENOB at OSR = 8. An improved version of a 2nd-order 9-bit NS SAR ADC is designed and simulated in a 40 nm process. The SNDR increases by 10 dB with OSR doubled, achieving a 14-bit ENOB at OSR = 16. At a bandwidth of 312.5 kHz, the Schreier FoM is 181 dB and the Walden FoM is 12.5 fJ/conversion-step, proving that the proposed NS SAR ADC architecture can achieve high resolution and high power efficiency simultaneously.Electrical and Computer Engineerin
Time interleaved counter analog to digital converters
The work explores extending time interleaving in A/D converters, by
applying a high-level of parallelism to one of the slowest and simplest types of
data-converters, the counter ADC. The motivation for the work is to realise
high-performance re-configurable A/D converters for use in multi-standard and
multi-PHY communication receivers with signal bandwidths in the 10s to 100s of
MHz. The counter ADC requires only a comparator, a ramp signal, and a
digital counter, where the comparator compares the sampled input against all
possible quantisation levels sequentially. This work explores arranging counter
ADCs in large time-interleaved arrays, building a Time Interleaved Counter
(TIC) ADC. The key to realising a TIC ADC is distributed sampling and a
global multi-phase ramp generator realised with a novel figure-of-8 rotating
resistor ring. Furthermore Counter ADCs allow for re-configurability between
effective sampling rate and resolution due to their sequential comparison of
reference levels in conversion. A prototype TIC ADC of 128-channels was
fabricated and measured in 0.13ÎŒm CMOS technology, where the same block can
be configured to operate as a 7-bit 1GS/s, 8-bit 500MS/s, or 9-bit 250MS/s dataconverter.
The ADC achieves a sub 400fJ/step FOM in all modes of
configuration
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