A 12GHz 30mW 130nm CMOS Rotary Travelling Wave Voltage Controlled Oscillator

This paper reports a 12GHz Rotary Travelling Wave (RTW) Voltage Controlled Oscillator designed in a 130nm CMOS technology. The phase noise and power consumption performances were compared with the literature and with telecommunication standards for broadcast satellite applications. The RTW VCO exhibits a -106dBc/Hz@1MHz and a 30mW power consumption with a sensibility of 400 MHz/V. Finally, requirements are given for a PLL implementation of the RTW VCO and simulated results are presented

Frequency Multipliers in SiGe BiCMOS for Local Oscillator Generation in D-band Wireless Transceivers

Communications at millimeter-wave (mm-Wave) have drawn a lot of attention in recent years due to the wide available bandwidth which translates directly to higher data transmission capacity. Generation of the transceivers local oscillation (LO) is critical because many contrasting requirements, i.e. tuning range (TR), phase noise (PN), output power, and level of spurious tones, affect the system performance. Differently from what is commonly pursued at Radio Frequency, LO generation with a PLL embedding a VCO at the desired output frequency is not viable at mm-wave. A more promising approach consists of a PLL in the 10-20GHz range, where silicon VCOs feature the best figure of merit, followed by a frequency multiplier. In this thesis, a frequency multiplication chain is investigated to up-convert an LO signal from X-band to D-band by a multiplication factor of 12. The multiplication is done in steps of 3, 2, and 2. A sextupler chip comprises the tripler and the first doubler and the last doubler stage which upconverts the LO signal from E- to D-band is realized in a separate chip, all in a 55nm SiGe BiCMOS technology. The frequency tripler circuit is based on a novel circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a separate break-out chip and consuming 23mW of DC power, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% fractional bandwidth and robustness to power variation of the driving signal over a 15dB range. Including the E-band doubler, the sextupler chip achieves a peak output power of 1.7dBm at 74.4GHz and remains within 2dB variation from 70GHz to 82GHz, corresponding to 16% fractional BW. In this frequency range, the leakages of all harmonics are suppressed by more than 40dBc. The design of the D-band doubler was aimed at delivering high output power with high efficiency and high conversion gain. Toward this end, the efficiency of a push-push pair was improved by a stacked Colpitts oscillator to boost the power conversion gain by 10dB. Moreover, the common-collector configuration keeps separate the oscillator tank from the load, allowing independent optimization of the harmonic conversion efficiency and the load impedance for maximum power delivery. The measured performance of the test chip demonstrated Pout up to 8dBm at 130GHz with 13dB conversion gain and 6.3% Power Added Efficiency

Quadrature Phase-Domain ADPLL with Integrated On-line Amplitude Locked Loop Calibration for 5G Multi-band Applications

5th generation wireless systems (5G) have expanded frequency band coverage with the low-band 5G and mid-band 5G frequencies spanning 600 MHz to 4 GHz spectrum. This dissertation focuses on a microelectronic implementation of CMOS 65 nm design of an All-Digital Phase Lock Loop (ADPLL), which is a critical component for advanced 5G wireless transceivers. The ADPLL is designed to operate in the frequency bands of 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz. Unique ADPLL sub-components include: 1) Digital Phase Frequency Detector, 2) Digital Loop Filter, 3) Channel Bank Select Circuit, and 4) Digital Control Oscillator. Integrated with the ADPLL is a 90-degree active RC-CR phase shifter with on-line amplitude locked loop (ALL) calibration to facilitate enhanced image rejection while mitigating the effects of fabrication process variations and component mismatch. A unique high-sensitivity high-speed dynamic voltage comparator is included as a key component of the active phase shifter/ALL calibration subsystem. 65nm CMOS technology circuit designs are included for the ADPLL and active phase shifter with simulation performance assessments. Phase noise results for 1 MHz offset with carrier frequencies of 600MHz, 2.4GHz, and 3.8GHz are -130, -122, and -116 dBc/Hz, respectively. Monte Carlo simulations to account for process variations/component mismatch show that the active phase shifter with ALL calibration maintains accurate quadrature phase outputs when operating within the frequency bands 600MHz-930MHz, 2.4GHz-2.8GHz and 3.4GHz-4.2GHz

The Expanded Very Large Array

In almost 30 years of operation, the Very Large Array (VLA) has proved to be a remarkably flexible and productive radio telescope. However, the basic capabilities of the VLA have changed little since it was designed. A major expansion utilizing modern technology is currently underway to improve the capabilities of the VLA by at least an order of magnitude in both sensitivity and in frequency coverage. The primary elements of the Expanded Very Large Array (EVLA) project include new or upgraded receivers for continuous frequency coverage from 1 to 50 GHz, new local oscillator, intermediate frequency, and wide bandwidth data transmission systems to carry signals with 16 GHz total bandwidth from each antenna, and a new digital correlator with the capability to process this bandwidth with an unprecedented number of frequency channels for an imaging array. Also included are a new monitor and control system and new software that will provide telescope ease of use. Scheduled for completion in 2012, the EVLA will provide the world research community with a flexible, powerful, general-purpose telescope to address current and future astronomical issues.Comment: Added journal reference: published in Proceedings of the IEEE, Special Issue on Advances in Radio Astronomy, August 2009, vol. 97, No. 8, 1448-1462 Six figures, one tabl

Millimeter-Wave and Terahertz Transceivers in SiGe BiCMOS Technologies

This invited paper reviews the progress of silicon–germanium (SiGe) bipolar-complementary metal–oxide–semiconductor (BiCMOS) technology-based integrated circuits (ICs) during the last two decades. Focus is set on various transceiver (TRX) realizations in the millimeter-wave range from 60 GHz and at terahertz (THz) frequencies above 300 GHz. This article discusses the development of SiGe technologies and ICs with the latter focusing on the commercially most important applications of radar and beyond 5G wireless communications. A variety of examples ranging from 77-GHz automotive radar to THz sensing as well as the beginnings of 60-GHz wireless communication up to THz chipsets for 100-Gb/s data transmission are recapitulated. This article closes with an outlook on emerging fields of research for future advancement of SiGe TRX performance

High Performance Local Oscillator Design for Next Generation Wireless Communication

Local Oscillator (LO) is an essential building block in modern wireless radios. In modern wireless radios, LO often serves as a reference of the carrier signal to modulate or demod- ulate the outgoing or incoming data. The LO signal should be a clean and stable source, such that the frequency or timing information of the carrier reference can be well-defined. However, as radio architecture evolves, the importance of LO path design has become much more important than before. Of late, many radio architecture innovations have exploited sophisticated LO generation schemes to meet the ever-increasing demands of wireless radio performances. The focus of this thesis is to address challenges in the LO path design for next-generation high performance wireless radios. These challenges include (1) Congested spectrum at low radio frequency (RF) below 5GHz (2) Continuing miniaturization of integrated wireless radio, and (3) Fiber-fast (>10Gb/s) mm-wave wireless communication. The thesis begins with a brief introduction of the aforementioned challenges followed by a discussion of the opportunities projected to overcome these challenges. To address the challenge of congested spectrum at frequency below 5GHz, novel ra- dio architectures such as cognitive radio, software-defined radio, and full-duplex radio have drawn significant research interest. Cognitive radio is a radio architecture that opportunisti- cally utilize the unused spectrum in an environment to maximize spectrum usage efficiency. Energy-efficient spectrum sensing is the key to implementing cognitive radio. To enable energy-efficient spectrum sensing, a fast-hopping frequency synthesizer is an essential build- ing block to swiftly sweep the carrier frequency of the radio across the available spectrum. Chapter 2 of this thesis further highlights the challenges and trade-offs of the current LO gen- eration scheme for possible use in sweeping LO-based spectrum analysis. It follows by intro- duction of the proposed fast-hopping LO architecture, its implementation and measurement results of the validated prototype. Chapter 3 proposes an embedded phase-shifting LO-path design for wideband RF self-interference cancellation for full-duplex radio. It demonstrates a synergistic design between the LO path and signal to perform self-interference cancellation. To address the challenge of continuing miniaturization of integrated wireless radio, ring oscillator-based frequency synthesizer is an attractive candidate due to its compactness. Chapter 4 discussed the difficulty associated with implementing a Phase-Locked Loop (PLL) with ultra-small form-factor. It further proposes the concept sub-sampling PLL with time- based loop filter to address these challenges. A 65nm CMOS prototype and its measurement result are presented for validation of the concept. In shifting from RF to mm-wave frequencies, the performance of wireless communication links is boosted by significant bandwidth and data-rate expansion. However, the demand for data-rate improvement is out-pacing the innovation of radio architectures. A >10Gb/s mm-wave wireless communication at 60GHz is required by emerging applications such as virtual-reality (VR) headsets, inter-rack data transmission at data center, and Ultra-High- Definition (UHD) TV home entertainment systems. Channel-bonding is considered to be a promising technique for achieving >10Gb/s wireless communication at 60GHz. Chapter 5 discusses the fundamental radio implementation challenges associated with channel-bonding for 60GHz wireless communication and the pros and cons of prior arts that attempted to address these challenges. It is followed by a discussion of the proposed 60GHz channel- bonding receiver, which utilizes only a single PLL and enables both contiguous and non- contiguous channel-bonding schemes. Finally, Chapter 6 presents the conclusion of this thesis

Study Of Design For Reliability Of Rf And Analog Circuits

Due to continued device dimensions scaling, CMOS transistors in the nanometer regime have resulted in major reliability and variability challenges. Reliability issues such as channel hot electron injection, gate dielectric breakdown, and negative bias temperature instability (NBTI) need to be accounted for in the design of robust RF circuits. In addition, process variations in the nanoscale CMOS transistors are another major concern in today‟s circuits design. An adaptive gate-source biasing scheme to improve the RF circuit reliability is presented in this work. The adaptive method automatically adjusts the gate-source voltage to compensate the reduction in drain current subjected to various device reliability mechanisms. A class-AB RF power amplifier shows that the use of a source resistance makes the power-added efficiency robust against threshold voltage and mobility variations, while the use of a source inductance is more reliable for the input third-order intercept point. A RF power amplifier with adaptive gate biasing is proposed to improve the circuit device reliability degradation and process variation. The performances of the power amplifier with adaptive gate biasing are compared with those of the power amplifier without adaptive gate biasing technique. The adaptive gate biasing makes the power amplifier more resilient to process variations as well as the device aging such as mobility and threshold voltage degradation. Injection locked voltage-controlled oscillators (VCOs) have been examined. The VCOs are implemented using TSMC 0.18 µm mixed-signal CMOS technology. The injection locked oscillators have improved phase noise performance than free running oscillators. iv A differential Clapp-VCO has been designed and fabricated for the evaluation of hot electron reliability. The differential Clapp-VCO is formed using cross-coupled nMOS transistors, on-chip transformers/inductors, and voltage-controlled capacitors. The experimental data demonstrate that the hot carrier damage increases the oscillation frequency and degrades the phase noise of Clapp-VCO. A p-channel transistor only VCO has been designed for low phase noise. The simulation results show that the phase noise degrades after NBTI stress at elevated temperature. This is due to increased interface states after NBTI stress. The process variability has also been evaluated

Lithium niobate RF-MEMS oscillators for IoT, 5G and beyond

This dissertation focuses on the design and implementation of lithium niobate (LiNbO3) radiofrequency microelectromechanical (RF-MEMS) oscillators for internet-of-things (IoT), 5G and beyond. The dissertation focuses on solving two main problems found nowadays in most of the published works: the narrow tuning range and the low operating frequency (sub 3 GHz) acoustic oscillators currently deliver. The work introduced here enables wideband voltage-controlled MEMS oscillators (VCMOs) needed for emerging applications in IoT. Moreover, it enables multi-GHz (above 8 GHz) RF-MEMS oscillators through harnessing over mode resonances for 5G and beyond. LiNbO3 resonators characterized by high-quality factor (Q), high electromechanical coupling (kt2), and high figure-of-merit (FoMRES= Q kt2) are crucial for building the envisioned high-performance oscillators. Those oscillators can be enabled with lower power consumption, wider tuning ranges, and a higher frequency of oscillation when compared to other state-of-the-art (SoA) RF-MEMS oscillators. Tackling the tuning range issue, the first VCMO based on the heterogeneous integration of a high Q LiNbO3 RF-MEMS resonator and complementary metal-oxide semiconductor (CMOS) is demonstrated in this dissertation. A LiNbO3 resonator array with a series resonance of 171.1 MHz, a Q of 410, and a kt2 of 12.7% is adopted, while the TSMC 65 nm RF LP CMOS technology is used to implement the active circuitry with an active area of 220×70 µm2. Frequency tuning of the VCMO is achieved by programming a binary-weighted digital capacitor bank and a varactor that are both connected in series to the resonator. The measured best phase noise performances of the VCMO are -72 and -153 dBc/Hz at 1 kHz and 10 MHz offsets from 178.23 and 175.83 MHz carriers, respectively. The VCMO consumes a direct current (DC) of 60 µA from a 1.2 V supply while realizing a tuning range of 2.4 MHz (~ 1.4% tuning range). Such VCMOs can be applied to enable ultralow-power, low phase noise, and wideband RF synthesis for emerging applications in IoT. Moreover, the first VCMO based on LiNbO3 lateral overtone bulk acoustic resonator (LOBAR) is demonstrated in this dissertation. The LOBAR excites over 30 resonant modes in the range of 100 to 800 MHz with a frequency spacing of 20 MHz. The VCMO consists of a LOBAR in a closed-loop with two amplification stages and a varactor-embedded tunable LC tank. By the bias voltage applied to the varactor, the tank can be tuned to change the closed-loop gain and phase responses of the oscillator so that Barkhausen’s conditions are satisfied for the targeted resonant mode. The tank is designed to allow the proposed VCMO to lock to any of the ten overtones ranging from 300 to 500 MHz. These ten tones are characterized by average Qs of 2100, kt2 of 1.5%, FoMRES of 31.5 enabling low phase noise, and low-power oscillators crucial for IoT. Owing to the high Qs of the LiNbO3 LOBAR, the measured VCMO shows a close-in phase noise of -100 dBc/Hz at 1 kHz offset from a 300 MHz carrier and a noise floor of -153 dBc/Hz while consuming 9 mW. With further optimization, this VCMO can lead to direct RF synthesis for ultra-low-power transceivers in multi-mode IoT nodes. Tackling the multi-GHz operation problem, the first Ku-band RF-MEMS oscillator utilizing a third antisymmetric overtone (A3) in a LiNbO3 resonator is presented in the dissertation. Quarter-wave resonators are used to satisfy Barkhausen’s oscillation conditions for the 3rd overtone while suppressing the fundamental and higher-order resonances. The oscillator achieves measured phase noise of -70 and -111 dBc/Hz at 1 kHz and 100 kHz offsets from a 12.9 GHz carrier while consuming 20 mW of dc power. The oscillator achieves a FoMOSC of 200 dB at 100 kHz offset. The achieved oscillation frequency is the highest reported to date for a MEMS oscillator. In addition, this dissertation introduces the first X-band RF-MEMS oscillator built using CMOS technology. The oscillator consists of an acoustic resonator in a closed loop with cascaded RF tuned amplifiers (TAs) built on TSMC RF GP 65 nm CMOS. The TAs bandpass response, set by on-chip inductors, satisfies Barkhausen's oscillation conditions for A3 only. Two circuit variations are implemented. The first is an 8.6 GHz standalone oscillator with a source-follower buffer for direct 50 Ω-based measurements. The second is an oscillator-divider chain using an on-chip 3-stage divide-by-2 frequency divider for a ~1.1 GHz output. The standalone oscillator achieves measured phase noise of -56, -113, and -135 dBc/Hz at 1 kHz, 100 kHz, and 1 MHz offsets from an 8.6 GHz output while consuming 10.2 mW of dc power. The oscillator also attains a FoMOSC of 201.6 dB at 100 kHz offset, surpassing the SoA electromagnetic (EM) and RF-MEMS based oscillators. The oscillator-divider chain produces a phase noise of -69.4 and -147 dBc/Hz at 1 kHz and 1 MHz offsets from a 1075 MHz output while consuming 12 mW of dc power. Its phase noise performance also surpasses the SoA L-band phase-locked loops (PLLs). The demonstrated performance shows the strong potential of microwave acoustic oscillators for 5G frequency synthesis and beyond. This work will enable low-power 5G transceivers featuring high speed, high sensitivity, and high selectivity in small form factors

Millimeter-Wave CMOS Digitally Controlled Oscillators for Automotive Radars

All-Digital-Phase-Locked-Loops (ADPLLs) are ideal for integrated circuit implementations and effectively generate frequency chirps for Frequency-Modulated-Continuous-Wave (FMCW) radar. This dissertation discusses the design requirements for integrated ADPLL, which is used as chirp synthesizer for FMCW automotive radar and focuses on an analysis of the ADPLL performance based on the Digitally-Controlled-Oscillator (DCO) design parameters and the ADPLL configuration. The fundamental principles of the FMCW radar are reviewed and the importance of linear DCO for reliable operation of the synthesizer is discussed. A novel DCO, which achieves linear frequency tuning steps is designed by arranging the available minimum Metal-Oxide-Metal (MoM) capacitor in unique confconfigurations. The DCO prototype fabricated in 65 nm CMOS fullls the requirements of the 77 GHz automotive radar. The resultant linear DCO characterization can effectively drive a chirp generation system in complete FMCW automotive radar synthesizer

SiGe-based broadband and high suppression frequency doubler ICs for wireless communications

制度:新 ; 報告番号:甲3419号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574