A Radiation hard bandgap reference circuit in a standard 0.13um CMOS Technology

With ongoing CMOS evolution, the gate-oxide thickness steadily decreases, resulting in an increased radiation tolerance of MOS transistors. Combined with special layout techniques, this yields circuits with a high inherent robustness against X-rays and other ionizing radiation. In bandgap voltage references, the dominant radiation-susceptibility is then no longer associated with the MOS transistors, but is dominated by the diodes. This paper gives an analysis of radiation effects in both MOSdevices and diodes and presents a solution to realize a radiation-hard voltage reference circuit in a standard CMOS technology. A demonstrator circuit was implemented in a standard 0.13 m CMOS technology. Measurements show correct operation with supply voltages in the range from 1.4 V down to 0.85 V, a reference voltage of 405 mV 7.5 mV ( = 6mVchip-to-chip statistical spread), and a reference voltage shift of only 1.5 mV (around 0.8%) under irradiation up to 44 Mrad (Si)

Near-Zero-Power Temperature Sensing via Tunneling Currents Through Complementary Metal-Oxide-Semiconductor Transistors.

Temperature sensors are routinely found in devices used to monitor the environment, the human body, industrial equipment, and beyond. In many such applications, the energy available from batteries or the power available from energy harvesters is extremely limited due to limited available volume, and thus the power consumption of sensing should be minimized in order to maximize operational lifetime. Here we present a new method to transduce and digitize temperature at very low power levels. Specifically, two pA current references are generated via small tunneling-current metal-oxide-semiconductor field effect transistors (MOSFETs) that are independent and proportional to temperature, respectively, which are then used to charge digitally-controllable banks of metal-insulator-metal (MIM) capacitors that, via a discrete-time feedback loop that equalizes charging time, digitize temperature directly. The proposed temperature sensor was integrated into a silicon microchip and occupied 0.15 mm2 of area. Four tested microchips were measured to consume only 113 pW with a resolution of 0.21 °C and an inaccuracy of ±1.65 °C, which represents a 628× reduction in power compared to prior-art without a significant reduction in performance

A system-on-chip digital pH meter for use in a wireless diagnostic capsule

This paper describes the design and implementation of a system-on-chip digital pH meter, for use in a wireless capsule application. The system is organized around an 8-bit microcontroller, designed to be functionally identical to the Motorola 6805. The analog subsystem contains a floating-electrode ISFET, which is fully compatible with a commercial CMOS process. On-chip programmable voltage references and multiplexors permit flexibility with the minimum of external connections. The chip is designed in a modular fashion to facilitate verification and component re-use. The single-chip pH meter can be directly connected to a personal computer, and gives a response of 37 bits/pH, within an operating range of 7 pH units

An Extended CMOS ISFET Model Incorporating the Physical Design Geometry and the Effects on Performance and Offset Variation

This paper presents an extended model for the CMOS-based ion-sensitive field-effect transistor, incorporating design parameters associated with the physical geometry of the device. This can, for the first time, provide a good match between calculated and measured characteristics by taking into account the effects of nonidealities such as threshold voltage variation and sensor noise. The model is evaluated through a number of devices with varying design parameters (chemical sensing area and MOSFET dimensions) fabricated in a commercially available 0.35-µm CMOS technology. Threshold voltage, subthreshold slope, chemical sensitivity, drift, and noise were measured and compared with the simulated results. The first- and second-order effects are analyzed in detail, and it is shown that the sensors' performance was in agreement with the proposed model

A neural probe with up to 966 electrodes and up to 384 configurable channels in 0.13 μm SOI CMOS

In vivo recording of neural action-potential and local-field-potential signals requires the use of high-resolution penetrating probes. Several international initiatives to better understand the brain are driving technology efforts towards maximizing the number of recording sites while minimizing the neural probe dimensions. We designed and fabricated (0.13-μm SOI Al CMOS) a 384-channel configurable neural probe for large-scale in vivo recording of neural signals. Up to 966 selectable active electrodes were integrated along an implantable shank (70 μm wide, 10 mm long, 20 μm thick), achieving a crosstalk of −64.4 dB. The probe base (5 × 9 mm2) implements dual-band recording and a 1

Spin-Based Neuron Model with Domain Wall Magnets as Synapse

We present artificial neural network design using spin devices that achieves ultra low voltage operation, low power consumption, high speed, and high integration density. We employ spin torque switched nano-magnets for modelling neuron and domain wall magnets for compact, programmable synapses. The spin based neuron-synapse units operate locally at ultra low supply voltage of 30mV resulting in low computation power. CMOS based inter-neuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics based models developed for the spin devices. Simulation results for character recognition as a benchmark application shows 95% lower power consumption as compared to 45nm CMOS design

Systematic Comparison of HF CMOS Transconductors

Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments

Generating All Two-MOS-Transistor Amplifiers Leads to New Wide-Band LNAs

This paper presents a methodology that systematically generates all 2-MOS-transistor wide-band amplifiers, assuming that MOSFET is exploited as a voltage-controlled current source. This leads to new circuits. Their gain and noise factor have been compared to well-known wide-band amplifiers. One of the new circuits appears to have a relatively low noise factor, which is also gain independent. Based on this new circuit, a 50-900 MHz variable-gain wide-band LNA has been designed in 0.35-µm CMOS. Measurements show a noise figure between 4.3 and 4.9 dB for gains from 6 to 11 dB. These values are more than 2 dB lower than the noise figure of the wide-band common-gate LNA for the same input matching, power consumption, and voltage gain. IIP2 and IIP3 are better than 23.5 and 14.5 dBm, respectively, while the LNA drains only 1.5 mA at 3.3 V