Analog Circuit Design in PD-SOI CMOS Technology for High Temperatures up to 400°C using Reverse Body Biasing (RBB)

This work focuses on analog integrated CMOS (Complementary Metal-Oxide-Semiconductor) circuit design in SOI (Silicon on Insulator) technology for the use in high temperature applications. It investigates the influence of reverse body biasing (RBB) on the analog characteristics of SOI-MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) transistors. Additionally, the enhancement of the operation capability of fundamental analog circuits at high temperatures up to 400°C with the use of RBB is investigated. Analog and digital integrated circuits are used in a variety of applications, e.g. consumer electronics or industrial measurement equipment. These integrated circuits have to work properly in the temperature range predefined by the application. As an example, operating temperatures reaching from −50°C to 250°C are required for geothermal drilling applications. Currently in the automotive industry, electronics have to operate reliably up to 150°C and as control electronics are placed closer to the engine, a much higher operating temperature is required. High temperature electronics are also used in avionic- and space applications, e.g. for future Venus exploration missions, where they have to withstand operating temperatures of 300°C to 500°C. Active or passive cooling of electronic components requires additional space and weight that increases the cost of the overall system. Cooling can be avoided in case electronics are capable of operating in harsh environmental conditions, i.e. at high temperatures. SOI-MOSFET devices are theoretically capable of operation up to 400°C or even higher, depending on the doping concentration of the silicon film. Nearly all material and device properties of importance to electronics worsen with increasing temperature, which is why 300°C to 350°C is the currently stated experimental maximum operating temperature of SOI devices. Analog circuit design up to the theoretical temperature limit exhibits severe limitations as SOI-MOSFET device characteristics are degenerated. SOI-MOSFET devices are partially depleted (PD) or fully depleted (FD), depending on the temperature, doping concentration of the silicon film, silicon film thickness and also channel length. FD devices offer a much better analog performance compared to their partially depleted counterparts and are preferred for analog circuit design. In the considered SOI technology, SOI- MOSFET devices are FD at low temperatures and PD at high temperatures. The transition from FD to PD at high temperatures leads to increased device leakage currents and hence reduces the overall performance of the transistor devices. Thereby, the gm/Id factor as a major figure of merit is decreased dramatically at high temperatures. Especially the moderate inversion region, which offers high intrinsic gain and moderate intrinsic bandwidth, is strongly affected as device leakage currents exceed the range of device operating currents at high temperatures. Reverse body biasing (RBB) refers to the reverse biasing of the film-source PN-junction of a MOSFET transistor. In recent works, reverse body biasing has been applied to digital circuits in order to reduce the static current consumption. Reverse body biasing has also been investigated in the analog domain. Nevertheless, the importance of the technique to realize analog circuits capable of operating at the theoretical temperature limit of SOI technology has not been identified yet. SOI-MOSFET devices with an H-shaped gate are investigated in a 1.0 µm PD-SOI technology. These devices provide a body-contact, which is used to apply the reverse body bias. It is found that due to the use of RBB, these devices remain fully depleted in the considered temperature range up to 400°C. Due to the reduction of leakage currents, reverse biased SOI-MOSFET devices are capable of operating in the mid moderate inversion region, with an operating current of one fifth of the leakage current level which was measured without RBB. This results in an improved gm/Id factor and an increase of the intrinsic gain by approximately 14 dB. Besides the investigation of SOI-MOSFET device characteristics, reverse body biasing is also applied to fundamental analog building blocks, e.g. an analog switch, current mirrors, a two-stage operational amplifier and a first order bandgap voltage reference. It is found that reverse body biasing significantly improves the high temperature operation of these circuits. In summary, the proposed technique of reverse body biasing offers the possibility to achieve FD device characteristics in a PD-SOI technology and thereby to improve the performance of analog circuits at high temperatures up to 400°C.Die vorliegende Arbeit ist im Bereich der analogen, integrierten CMOS (Complementary Metal-Oxide-Semiconductor) Schaltungstechnik in SOI (Silicon on Insulator) Technologie für den Einsatz in Hochtemperaturanwendungen angesiedelt. Ausgehend von der Untersuchung analoger Transistoreigenschaften von SOI-MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) Transistoren unter Verwendung von RBB (Reverse body biasing), wird zusätzlich die verbesserte Hochtemperaturtauglichkeit grundlegender analoger Schaltungen bis 400°C unter dem Einfluss von RBB untersucht. Analoge und digitale integrierte Schaltungen werden in einer Vielzahl von Anwendungen, wie z. B. in der Unterhaltungselektronik oder der industriellen Messtechnik eingesetzt. Dabei müssen diese Schaltungen in dem für die Anwendung spezifizierten Temperaturbereich zuverlässig arbeiten. Beispielsweise werden elektronische Bauelemente in einem Temperaturbereich von −50°C bis 250°C zur Durchführung geo-thermischer Bohrungen eingesetzt. In der Automobilindustrie müssen integrierte Schaltungen bis zu einer Temperatur von 150°C zuverlässig arbeiten, wobei durch die Platzierung der Steuerelektronik in unmittelbarer Nähe zum Motor künftig weiter steigende Betriebstemperaturen erforderlich werden. Die Hochtemperaturelektronik findet ebenfalls Anwendung in der Luft- und Raumfahrt. Bei der zukünftigen Erkundung der Venus beispielsweise, müssen Umgebungstemperaturen von 300°C-500°C von allen Systemkomponenten unbeschadet überstanden werden. Die aktive oder passive Kühlung integrierter, elektronischer Komponenten erfordert zusätzlich Platz und Gewicht, und erhöht somit die Kosten des Gesamtsystems. Dabei kann die Kühlung elektronischer Komponenten vermieden werden, wenn diese in der Lage sind, bei hohen Umgebungstemperaturen zu arbeiten. SOI-MOSFET Transistoren können theoretisch bei Umgebungstemperaturen bis zu 400°C und höher betrieben werden. Diese Temperaturobergrenze wird stark durch die Dotierstoffkonzentration im Siliziumfilm und der Siliziumfilmdicke bestimmt. Da nahezu alle wesentlichen Material- und Leistungseigenschaften integrierter Schaltungen durch steigende Umgebungstemperaturen negativ beeinflusst werden, liegt die momentane Temperaturobergrenze von SOI-basierten Hochtemperaturschaltungen im Bereich der praktischen Anwendung daher lediglich bei 300°C bis 350°C. Somit werden die Möglichkeiten zur Realisierung integrierter Schaltungen über diese Grenze hinaus durch die Degeneration der Transistoreigenschaften bei hohen Temperaturen limitiert. Abhängig von der Temperatur, der Dotierstoffkonzentration im Siliziumfilm, der Siliziumfilmdicke und der Kanallänge, sind die Transistoren teilweise verarmt (partially depleted, PD) oder vollständig verarmt (fully depleted, FD). FD Transistoren weisen deutlich verbesserte Analogeigenschaften auf als PD Transistoren und werden aus diesem Grund bevorzugt eingesetzt. In der untersuchten SOI Technologie ändern SOI-MOSFET Transistoren ihren Verarmungszustand von FD bei niedrigen Temperaturen zu PD bei hohen Temperaturen. Der Zustand der teilweisen Verarmung führt zum Anstieg von Leckströmen innerhalb der Transistoren und damit zur Degeneration der analogen Transistoreigenschaften. Reverse body biasing bezeichnet den Betrieb von MOSFET Transistoren mit einem in Sperrrichtung betriebenen Film-Source PN-Übergang. In bisherigen Arbeiten wurde RBB dazu eingesetzt, das Leckstromverhalten digitaler integrierter Schaltungen zu verbessern und unter anderem um die Durchbruchspannung der Transistoren zu beeinflussen. Die Auswirkungen dieser Methode auf die analogen Eigenschaften von SOI-MOSFET Transistoren und den Betrieb analoger Schaltungen bei hohen Temperaturen wurden jedoch bislang nicht ausreichend untersucht. In dieser Arbeit werden HGATE SOI-MOSFET Transistoren in einer 1.0 µm PD-SOI CMOS Technologie untersucht. Diese Transistoren zeichnen sich durch eine H-förmige Gate-Elektrode sowie einen separaten Filmkontakt aus, welcher zur Anwendung von RBB verwendet wird. Es zeigt sich, dass der Verarmungszustand der Transistoren durch die Anwendung von RBB bei hohen Temperaturen positiv beeinflusst werden kann. So bleiben die untersuchen Transistoren im betrachteten Temperaturbereich bis 400°C vollständig verarmt. Durch die deutliche Reduzierung der Leckströme ist es möglich, die Transistoren bis 400°C im Arbeitspunkt der moderaten Inversion zu betreiben. Dabei kann der Betriebsstrom der Transistoren bis auf ein Fünftel des vorherigen Leckstromniveaus reduziert werden, was zu einer wesentlichen Verbesserung des gm/Id Faktors und einem Anstieg der intrinsischen Verstärkung um ca. 14 dB führt. Neben der Untersuchung der SOI-MOSFET Transistoreigenschaften wurde zudem der Einfluss von RBB auf die Hochtemperaturtauglichkeit grundlegender analoger Schaltungsblöcke, wie z. B. analoger Schalter, Stromspiegel, zweistufiger Operationsverstärker und Bandgap Spannungsreferenzen untersucht. Es zeigt sich, dass sich die Hochtemperaturtauglichkeit dieser Schaltungen durch den Einsatz von RBB maßgeblich verbessern lässt. Zusammengefasst werden durch die Anwendung von RBB in einer PD-SOI Technologie FD-SOI Transistoreigenschaften erzielt, die den Betrieb analoger Schaltungen bis 400°C ermöglichen

Phase Noise Analyses and Measurements in the Hybrid Memristor-CMOS Phase-Locked Loop Design and Devices Beyond Bulk CMOS

Phase-locked loop (PLLs) has been widely used in analog or mixed-signal integrated circuits. Since there is an increasing market for low noise and high speed devices, PLLs are being employed in communications. In this dissertation, we investigated phase noise, tuning range, jitter, and power performances in different architectures of PLL designs. More energy efficient devices such as memristor, graphene, transition metal di-chalcogenide (TMDC) materials and their respective transistors are introduced in the design phase-locked loop. Subsequently, we modeled phase noise of a CMOS phase-locked loop from the superposition of noises from its building blocks which comprises of a voltage-controlled oscillator, loop filter, frequency divider, phase-frequency detector, and the auxiliary input reference clock. Similarly, a linear time-invariant model that has additive noise sources in frequency domain is used to analyze the phase noise. The modeled phase noise results are further compared with the corresponding phase-locked loop designs in different n-well CMOS processes. With the scaling of CMOS technology and the increase of the electrical field, the problem of short channel effects (SCE) has become dominant, which causes decay in subthreshold slope (SS) and positive and negative shifts in the threshold voltages of nMOS and pMOS transistors, respectively. Various devices are proposed to continue extending Moore\u27s law and the roadmap in semiconductor industry. We employed tunnel field effect transistor owing to its better performance in terms of SS, leakage current, power consumption etc. Applying an appropriate bias voltage to the gate-source region of TFET causes the valence band to align with the conduction band and injecting the charge carriers. Similarly, under reverse bias, the two bands are misaligned and there is no injection of carriers. We implemented graphene TFET and MoS2 in PLL design and the results show improvements in phase noise, jitter, tuning range, and frequency of operation. In addition, the power consumption is greatly reduced due to the low supply voltage of tunnel field effect transistor

InP-based membrane photodetectors on Si photonic circuitry

The work presented in this thesis is about indium phosphide (InP) based photodetectors for use in optical interconnections on silicon (Si) integrated circuits (ICs). The motivation for this work comes from the bottleneck expected at the interconnect level for future generation electronic ICs: with the technology scaling down and the signal switching frequency increasing, three main issues are predicted for the complementary metal-oxide semiconductor (CMOS) ICs, namely signal propagation delay, power consumption and integration density. Electrical interconnects (EIs) strongly limit these characteristics and a promising solution is given by replacing EIs with optical interconnects (OIs). The implementation of intra-chip and chip-to-chip OIs requires the use of photonic integrated circuit (PIC) technology. The integration of optical sources, waveguides and detectors forming a photonic interconnect layer on top of the CMOS circuitry provides bandwidth increase, immunity to electromagnetic (EM) noise and reduction in power consumption. This solution was investigated within this work, which focuses on the detector part. InP-based membrane photodetectors were realized on InP dies bonded on Si and CMOS wafers, on top of which passive Si and Si3N4 photonic circuitry had been defined. This approach combines the advantages of high quality Si-based passive circuits with the excellent properties of InP-based components for light generation and detection. The technology used for the InP device fabrication is compatible with wafer scale processing steps, assuring compatibility towards future generation electronic ICs. The major results of this work are summarized as follows: InP membrane couplers and detectors were successfully fabricated on Si and Si3N4 photonic circuits. Experimental results show working active and passive devices, namely: passive Si photonic components (waveguides, MMIs, (de)-multiplexers), InP membrane couplers, InP-based detectors and heterogeneously integrated multiwavelength receivers. A working laser-to-detector integrated optical link on Si was successfully demonstrated. This work was carried out with the support of the European project IST-PICMOS and of the Dutch Ministry of Economic Affairs through the Smartmix Memphis project

Robust Design With Increasing Device Variability In Sub-Micron Cmos And Beyond: A Bottom-Up Framework

My Ph.D. research develops a tiered systematic framework for designing process-independent and variability-tolerant integrated circuits. This bottom-up approach starts from designing self-compensated circuits as accurate building blocks, and moves up to sub-systems with negative feedback loop and full system-level calibration. a. Design methodology for self-compensated circuits My collaborators and I proposed a novel design methodology that offers designers intuitive insights to create new topologies that are self-compensated and intrinsically process-independent without external reference. It is the first systematic approaches to create "correct-by-design" low variation circuits, and can scale beyond sub-micron CMOS nodes and extend to emerging non-silicon nano-devices. We demonstrated this methodology with an addition-based current source in both 180nm and 90nm CMOS that has 2.5x improved process variation and 6.7x improved temperature sensitivity, and a GHz ring oscillator (RO) in 90nm CMOS with 65% reduction in frequency variation and 85ppm/oC temperature sensitivity. Compared to previous designs, our RO exhibits the lowest temperature sensitivity and process variation, while consuming the least amount of power in the GHz range. Another self-compensated low noise amplifiers (LNA) we designed also exhibits 3.5x improvement in both process and temperature variation and enhanced supply voltage regulation. As part of the efforts to improve the accuracy of the building blocks, I also demonstrated experimentally that due to "diversification effect", the upper bound of circuit accuracy can be better than the minimum tolerance of on-chip devices (MOSFET, R, C, and L), which allows circuit designers to achieve better accuracy with less chip area and power consumption. b. Negative feedback loop based sub-system I explored the feasibility of using high-accuracy DC blocks as low-variation "rulers-on-chip" to regulate high-speed high-variation blocks (e.g. GHz oscillators). In this way, the trade-off between speed (which can be translated to power) and variation can be effectively de-coupled. I demonstrated this proposed structure in an integrated GHz ring oscillators that achieve 2.6% frequency accuracy and 5x improved temperature sensitivity in 90nm CMOS. c. Power-efficient system-level calibration To enable full system-level calibration and further reduce power consumption in active feedback loops, I implemented a successive-approximation-based calibration scheme in a tunable GHz VCO for low power impulse radio in 65nm CMOS. Events such as power-up and temperature drifts are monitored by the circuits and used to trigger the need-based frequency calibration. With my proposed scheme and circuitry, the calibration can be performed under 135pJ and the oscillator can operate between 0.8 and 2GHz at merely 40[MICRO SIGN]W, which is ideal for extremely power-and-cost constraint applications such as implantable biomedical device and wireless sensor networks

Impacts of Cmos Scaling on the Analog Design

The advancement of the CMOS fabrication process has pushed the CMOS transistor scaling to the sub-100nm node. While process fabrication and logic designers advocated CMOS scaling consistent with Moore's Law, circuit engineers are struggling with the high leakage current, low power supply, and high power consumption. For the analog circuit designer, things become even worse due to the loss in dynamic range.The objective of this research was to investigate the impacts of the CMOS scaling on the analog design and proposed analog scaling rule: the overdrive voltage should scale at the same rate or faster than the supply voltage to maintain a power settling product efficiency which is constant or improving. To avoid a power consumption penalty, the final specifications for the analog power supply will stall at a voltage of near 1.1V, with an overdrive voltage of 0.1V. Device thresholds must be limited to an approximate voltage 0.3V for analog designs. Due to the reducing self-gain of the transistor from the scaling, multistage OTA topologies should be adopted to achieve high gain and high bandwidth. Different OTA topologies were analyzed in close loop form and compared based on a power settling product efficiency criteria. The nested gain boosted cascode OTA topology was found to have the best efficiency under high supply voltage, high overdrive voltage or low supply voltage, low overdrive voltage. Finally, a 2V 20Msample/s 11-bit pipelined ADC was designed as an example to demonstrate the benefits of the nested cascode OTA application to low voltage pipelined ADC design. The size of the ADC stages was optimally scaled to achieve low power consumption. The full ADC was simulated on the behavior model level by using Matlab Simulink. Cadence simulations and the Peregrine 0.5um SOS device models were used to verify critical components of the ADC further demonstrating feasibility.Electrical Engineering Technolog

Addressing On-Chip Power Conversion and Dissipation Issues in Many-Core System-on-a-Chip based on Conventional Silicon and Emerging Nanotechnologies

Title from PDF of title page viewed August 27, 2018Dissertation advisor: Masud H ChowdhuryVitaIncludes bibliographical references (pages 158-163)Thesis (Ph.D.)--School of Computing and Engineering and Department of Physics and Astronomy. University of Missouri--Kansas City, 2017Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip regulator design very unattractive for SOC integration and multi-/many-core environments. To circumvent the challenges, three alternative techniques based on active circuit elements to replace the passive LC filter of the buck convertor are developed. The first inductorless on-chip switching voltage regulator architecture is based on a cascaded 2nd order multiple feedback (MFB) low-pass filter (LPF). This design has the ability to modulate to multiple voltage settings via pulse with modulation (PWM). The second approach is a supplementary design utilizing a hybrid low drop-out scheme to lower the output ripple of the switching regulator over a wider frequency range. The third design approach allows the integration of an entire power management system within a single chipset by combining a highly efficient switching regulator with an intermittently efficient linear regulator (area efficient), for robust and highly efficient on-chip regulation. The static power (Pstatic) or subthreshold leakage power (Pleak) increases with technology scaling. To mitigate static power dissipation, power gating techniques are implemented. Power gating is one of the popular methods to manage leakage power during standby periods in low-power high-speed IC design. It works by using transistor based switches to shut down part of the circuit block and put them in the idle mode. The efficiency of a power gating scheme involves minimum Ioff and high Ion for the sleep transistor. A conventional sleep transistor circuit design requires an additional header, footer, or both switches to turn off the logic block. This additional transistor causes signal delay and increases the chip area. We propose two innovative designs for next generation sleep transistor designs. For an above threshold operation, we present a sleep transistor design based on fully depleted silicon-on-insulator (FDSOI) device. For a subthreshold circuit operation, we implement a sleep transistor utilizing the newly developed silicon-on ferroelectric-insulator field effect transistor (SOFFET). In both of the designs, the ability to control the threshold voltage via bias voltage at the back gate makes both devices more flexible for sleep transistors design than a bulk MOSFET. The proposed approaches simplify the design complexity, reduce the chip area, eliminate the voltage drop by sleep transistor, and improve power dissipation. In addition, the design provides a dynamically controlled Vt for times when the circuit needs to be in a sleep or switching mode.Introduction -- Background and literature review -- Fully integrated on-chip switching voltage regulator -- Hybrid LDO voltage regulator based on cascaded second order multiple feedback loop -- Single and dual output two-stage on-chip power management system -- Sleep transistor design using double-gate FDSOI -- Subthreshold region sleep transistor design -- Conclusio

Current-mode processing based Temperature-to-Digital Converters for MEMS applications

This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results.This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results