164-GHz MMIC HEMT Frequency Doubler

A monolithic microwave integrated circuit (MMIC) that includes a high-electron-mobility transistor (HEMT) has been developed as a prototype of improved frequency doublers for generating signals at frequencies greater than 100 GHz. Signal sources that operate in this frequency range are needed for a variety of applications, notably including general radiometry and, more specifically, radiometric remote sensing of the atmosphere. Heretofore, it has been common practice to use passive (diode-based) frequency multipliers to obtain frequencies greater than 100 GHz. Unfortunately, diode-based frequency multipliers are plagued by high DC power consumption and low conversion efficiency. Moreover, multiplier diodes are not easily integrated with such other multiplier-circuit components as amplifiers and oscillators. The goals of developing the present MMIC HEMT frequency doubler were (1) to utilize the HEMT as an amplifier to increase conversion efficiency (more precisely, to reduce conversion loss), thereby increasing the output power for a given DC power consumption or, equivalently, reducing the DC power consumption for a given output power; and (2) to provide for the integration of amplifier and oscillator components on the same chip. The MMIC frequency doubler (see Figure 1) contains an AlInAs/GaInAs/InP HEMT biased at pinch-off to make it function as a class-B amplifier (meaning that it conducts in half-cycle pulses). Grounded coplanar waveguides (GCPWs) are used as impedance-matching transmission lines. Air bridges are placed at discontinuities to suppress undesired slot electromagnetic modes. Another combination of GCPWs also serves both as a low-pass filter to suppress undesired oscillations at frequencies below 60 GHz and as a DC blocker. Large decoupling capacitors and epitaxial resistors are added in the drain and gate lines to suppress bias oscillations. At the output terminal, the fundamental frequency is suppressed by a quarter-wave open stub, which presents a short circuit at the fundamental frequency and an open circuit at the second harmonic. At an input power of 7 mW, the output power and conversion loss at an output frequency of 164 GHz were found to be 5 dBm (approximately equal to 3.2 mW) and 2 dB, respectively, with a 3-dB output-power bandwidth of 14 GHz. This is the best performance reported to date for an MMIC HEMT frequency doubler above 100 GHz

Study of quasi-optical circuit techniques in varactor multipliers

Quasi-optical circuit techniques in varactor multiplier

Efficient generation of highly squeezed light and second harmonic wave with periodically poled MgO:LiNbO_3

We report on effective generation of continuous-wave squeezed light and second harmonics with a periodically poled MgO:LiNbO$_{\mathrm{3}}$ (PPMgLN) crystal which enables us to utilize the large nonlinear optical coefficient $d_{\mathrm{33}}$. We achieved the squeezing level of $-7.60 \pm 0.15$dB at 860 nm by utilizing a subthreshol optical parametric oscillator with a PPMgLN crystal. We also generated 400 mW of second harmonics at 430 nm from 570 mW of fundamental waves with 70% of conversion efficiency by using a PPMgLN crystal inside an external cavity.Comment: 4 pages, 3 figure

SiGe-based broadband and high suppression frequency doubler ICs for wireless communications

制度:新 ; 報告番号:甲3419号 ; 学位の種類:博士(工学) ; 授与年月日:2011/9/15 ; 早大学位記番号:新574

Design And Implementation Of Millimeter Wave Frequency Multiplier In 65Nm Rf Cmos Technology

In this thesis, the design and implementation of frequency multipliers in 65nm CMOS was explored for millimeter wave oscillators and optimized to achieve higher output power and better rejection of the fundamental frequency. Several types of frequency multipliers are discussed. Transformers for AC-coupling used in the frequency multipliers were also explored. The design and optimization of the circuits was performed using Sonnet, Cadence, and ADS software tools. In this work the design of a frequency multiplier which takes in a 12.5GHz signal and outputs 100GHz at the output is achieved. Three transformers are used for three stages of a frequency doubler to achieve a multiplication by eight. High isolation is achieved between the input frequency and the output. The output power level is –4dBm. The fundamental rejection is above 35dB. The power consumed by this frequency multiplier is 18mW. While multiplication of up to 4 is achieved in CMOS devices in other works, we are able to achieve a frequency multiplication of 8 in this work

Design And Implementation Of Millimeter Wave Frequency Multiplier In 65Nm Rf Cmos Technology

In this thesis, the design and implementation of frequency multipliers in 65nm CMOS was explored for millimeter wave oscillators and optimized to achieve higher output power and better rejection of the fundamental frequency. Several types of frequency multipliers are discussed. Transformers for AC-coupling used in the frequency multipliers were also explored. The design and optimization of the circuits was performed using Sonnet, Cadence, and ADS software tools. In this work the design of a frequency multiplier which takes in a 12.5GHz signal and outputs 100GHz at the output is achieved. Three transformers are used for three stages of a frequency doubler to achieve a multiplication by eight. High isolation is achieved between the input frequency and the output. The output power level is –4dBm. The fundamental rejection is above 35dB. The power consumed by this frequency multiplier is 18mW. While multiplication of up to 4 is achieved in CMOS devices in other works, we are able to achieve a frequency multiplication of 8 in this work

Quadrature LC VCO with passive coupling and phase combining network

A circuit and method for generating a signal is disclosed. The circuit includes a set of wide tuning LC tanks, a set of core transistors cross coupled to the set of wide tuning LC tanks, and a combining network coupled to the set of wide tuning LC tanks and the set of core transistors. The combining network further includes a set of inputs connected to the set of wide tuning LC tanks and the set of core transistors, a set of coupling transistors connected to the set of inputs, a set of source inductors connected to the set of coupling transistors, a coupling capacitor connected to the set of source inductors, a load resistor connected to the coupling capacitor. The combining network combines the set of inputs and the signal is delivered to the load resistor as a fourth order harmonic.Board of Regents, University of Texas Syste

Design of 300 ghz combined doubler/subharmonic mixer based on schottky diodes with integrated mmic based local oscillator

In this paper the design and experimental characterization of a combined doublersubharmonic mixer based on Schottky diodes which uses a 75 GHz MMIC based local oscillator is presented. This solution integrates in the same substrate the doubler and the mixer, which share the same metallic packaging with the local oscillator. The prototype has been fabricated and measured. For characterization, the Y-Factor technique has been used and the prototype yields a best conversion loss and equivalent noise temperature of 11 dB and 1976 K, respectively, at 305 GHz. This performance is close to the state of the art, and shows the potential of this approach, which allows a significant reduction in terms of size and volume.This research was funded by the Spanish MINECO, Project No. TEC2016-76997-C3-1-R, and by the Spanish State Research Agency, Project No. PID2019-109984RB-C43/AEI/10.13039/501100011033