Parallel Machines and Algorithms for Discrete-Event Simulations

A number of recent articles have focused on the design of high speed discrete-event simulation (DES) machines for digital logic simulation. These investigations are in response to the enormous costs associated with the simulation of complex (VLSI) digital circuits for logic verification and fault analysis. One approach to reducing simulation costs is to design special purpose digital computers that are tailored to the logic simulation test. This paper is concerned with the architecture of such logic machines. The paper has three principal parts. First, a taxonomy of logic machine architectures is presented. The taxonomy focuses on the central components of the logic simulation algorithms and on architectural alternatives for increasing the speed of the simulation process. It thus represents a basis for discussing and differentiating between proposed architectures and also results in the identification of several new architectures. Although developed for digital logic simulators., the taxonomy can be used for general DES machines. Second, a performance measure is presented which permits evaluation of DES machines. Finally several DES machine designs are described and categorized using the taxonomy

Logic Simulation: Statistics and Machine Design

The high costs associated with logic simulation of large VLSI based systems have led to the need for new computer architectures tailored to the simulation task. Such architecture have the potential for significant speed-ups over standard software based logic simulators. Several commercial simulation engines have bene produced to satisfy needs in this area. To properly explore the space of alternative simulation architectures, data is required on the simulation process itself. This paper presents a framework for such data gathering activity and uses the data in estimating the maximum speed-up attainable with a particular type of special-purpose parallel/pipelined simulation machine. First, possible sources of speed-up in the logic simulation task are examined. Then, the sort of data needed in the design of simulation engines is discussed. Next, the data is presented and the implication on machine design are discussed. This data includes information on subtask times found in standard discrete-event simulation algorithms, event intensities, queue length distributions, and simultaneous event distributions. Finally, a simple performance model of one type of simulation machine is developed, and the maximum speed-up attainable with this type of machine is predicted

Logic Simulation using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine

The Chandy-Misra-Bryant (CMB) model has been applied to logic simulation of synchronous sequential circuits using a massively parallel SIMD computer, a CM-2 Connection Machine. Several methods of reducing message traffic in a logic simulation have been adapted to the SIMD architecture of the CM-2, with the result that each method of reducing message traffic actually decreases the speed of the simulation. This suggests that communication costs required to support logic simulation are small compared to the cost of deciding which messages need not be sent

On efficient simulations of multicounter machines

An oblivious 1-tape Turing machine can simulate a multicounter machine on-line in linear time and logarithmic space. This leads to a linear cost combinational logic network implementing the first n steps of a multicounter machine and also to a linear time/logarithmic space on-line simulation by an oblivious logarithmic cost RAM. An oblivious log*n-head tape unit can simulate the first n steps of a multicounter machine in real-time, which leads to a linear cost combinational logic network with a constant data rate

Universality and programmability of quantum computers

Manin, Feynman, and Deutsch have viewed quantum computing as a kind of universal physical simulation procedure. Much of the writing about quantum logic circuits and quantum Turing machines has shown how these machines can simulate an arbitrary unitary transformation on a finite number of qubits. The problem of universality has been addressed most famously in a paper by Deutsch, and later by Bernstein and Vazirani as well as Kitaev and Solovay. The quantum logic circuit model, developed by Feynman and Deutsch, has been more prominent in the research literature than Deutsch's quantum Turing machines. Quantum Turing machines form a class closely related to deterministic and probabilistic Turing machines and one might hope to find a universal machine in this class. A universal machine is the basis of a notion of programmability. The extent to which universality has in fact been established by the pioneers in the field is examined and this key notion in theoretical computer science is scrutinised in quantum computing by distinguishing various connotations and concomitant results and problems.Comment: 17 pages, expands on arXiv:0705.3077v1 [quant-ph

Performance Analysis and Design of a Logic Simulation Machine

The high costs associated with logic simulation of large VLSI based circuits has led to the need for new computer architecture tailored to the simulation task. Such architectures have the potential for significant speed-ups over software-based logic simulators executing on standard sequential computers. This paper presents a model of one class of multiprocessor simulation architectures and compares the performance of some of these machines using data obtained from simulation of VLSI circuits. In addition, we discuss the implications of our results on machine design and examine the sensitivity of the model to variations in circuit characteristics

An experimental laboratory bench setup to study electric vehicle antilock braking / traction systems and their control

This paper describes the preliminary research and implementation of an experimental test bench set up for an electric vehicle antilock braking system (ABS)/traction control system (TCS) representing the dry, wet and icy road surfaces. A fuzzy logic based controller to control the wheel slip for electric vehicle antilock braking system is presented. The test facility comprised of an induction machine load operating in the generating region. The test facility was used to simulate a variety of tire/road μ-σ driving conditions, eliminating the initial requirement for skid-pan trials when developing algorithms. Simulation studies and results are provided