2,047 research outputs found
Logic synthesis and testing techniques for switching nano-crossbar arrays
Beyond CMOS, new technologies are emerging to extend electronic systems with features unavailable to silicon-based devices. Emerging technologies provide new logic and interconnection structures for computation, storage and communication that may require new design paradigms, and therefore trigger the development of a new generation of design automation tools. In the last decade, several emerging technologies have been proposed and the time has come for studying new ad-hoc techniques and tools for logic synthesis, physical design and testing. The main goal of this project is developing a complete synthesis and optimization methodology for switching nano-crossbar arrays that leads to the design and construction of an emerging nanocomputer. New models for diode, FET, and four-terminal switch based nanoarrays are developed. The proposed methodology implements logic, arithmetic, and memory elements by considering performance parameters such as area, delay, power dissipation, and reliability. With combination of logic, arithmetic, and memory elements a synchronous state machine (SSM), representation of a computer, is realized. The proposed methodology targets variety of emerging technologies including nanowire/nanotube crossbar arrays, magnetic switch-based structures, and crossbar memories. The results of this project will be a foundation of nano-crossbar based circuit design techniques and greatly contribute to the construction of emerging computers beyond CMOS. The topic of this project can be considered under the research area of Ăą\u80\u9cEmerging Computing ModelsĂą\u80\u9d or Ăą\u80\u9cComputational NanoelectronicsĂą\u80\u9d, more specifically the design, modeling, and simulation of new nanoscale switches beyond CMOS
Template-based embedded reconfigurable computing
XIV+212hlm.;24c
Containing the Nanometer âPandora-Boxâ: Cross-Layer Design Techniques for Variation Aware Low Power Systems
The demand for richer multimedia services, multifunctional portable devices and high data rates can only been visioned due to the improvement in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scalingâparameter variations, that threaten the correct operation of circuits, and increased energy consumption, that limits the operational lifetime of todayâs systems. The contradictory design requirements for low-power and system robustness, is one of the most challenging design problems of today. The design efforts are further complicated due to the heterogeneous types of designs (logic, memory, mixed-signal) that are included in todayâs complex systems and are characterized by different design requirements. This paper presents an overview of techniques at various levels of design abstraction that lead to low power and variation aware logic, memory and mixed-signal circuits and can potentially assist in meeting the strict power budgets and yield/quality requirements of future systems
Embedded electronic systems driven by run-time reconfigurable hardware
Abstract
This doctoral thesis addresses the design of embedded electronic systems based on run-time reconfigurable hardware technology âavailable through SRAM-based FPGA/SoC devicesâ aimed at contributing to enhance the life quality of the human beings. This work does research on the conception of the system architecture and the reconfiguration engine that provides to the FPGA the capability of dynamic partial reconfiguration in order to synthesize, by means of hardware/software co-design, a given application partitioned in processing tasks which are multiplexed in time and space, optimizing thus its physical implementation âsilicon area, processing time, complexity, flexibility, functional density, cost and power consumptionâ in comparison with other alternatives based on static hardware (MCU, DSP, GPU, ASSP, ASIC, etc.). The design flow of such technology is evaluated through the prototyping of several engineering applications (control systems, mathematical coprocessors, complex image processors, etc.), showing a high enough level of maturity for its exploitation in the industry.Resumen
Esta tesis doctoral abarca el diseño de sistemas electrĂłnicos embebidos basados en tecnologĂa hardware dinĂĄmicamente reconfigurable âdisponible a travĂ©s de dispositivos lĂłgicos programables SRAM FPGA/SoCâ que contribuyan a la mejora de la calidad de vida de la sociedad. Se investiga la arquitectura del sistema y del motor de reconfiguraciĂłn que proporcione a la FPGA la capacidad de reconfiguraciĂłn dinĂĄmica parcial de sus recursos programables, con objeto de sintetizar, mediante codiseño hardware/software, una determinada aplicaciĂłn particionada en tareas multiplexadas en tiempo y en espacio, optimizando asĂ su implementaciĂłn fĂsica âĂĄrea de silicio, tiempo de procesado, complejidad, flexibilidad, densidad funcional, coste y potencia disipadaâ comparada con otras alternativas basadas en hardware estĂĄtico (MCU, DSP, GPU, ASSP, ASIC, etc.). Se evalĂșa el flujo de diseño de dicha tecnologĂa a travĂ©s del prototipado de varias aplicaciones de ingenierĂa (sistemas de control, coprocesadores aritmĂ©ticos, procesadores de imagen, etc.), evidenciando un nivel de madurez viable ya para su explotaciĂłn en la industria.Resum
Aquesta tesi doctoral estĂ orientada al disseny de sistemes electrĂČnics empotrats basats en tecnologia hardware dinĂ micament reconfigurable âdisponible mitjançant dispositius lĂČgics programables SRAM FPGA/SoCâ que contribueixin a la millora de la qualitat de vida de la societat. Sâinvestiga lâarquitectura del sistema i del motor de reconfiguraciĂł que proporcioni a la FPGA la capacitat de reconfiguraciĂł dinĂ mica parcial dels seus recursos programables, amb lâobjectiu de sintetitzar, mitjançant codisseny hardware/software, una determinada aplicaciĂł particionada en tasques multiplexades en temps i en espai, optimizant aixĂ la seva implementaciĂł fĂsica âĂ rea de silici, temps de processat, complexitat, flexibilitat, densitat funcional, cost i potĂšncia dissipadaâ comparada amb altres alternatives basades en hardware estĂ tic (MCU, DSP, GPU, ASSP, ASIC, etc.). SâevalĂșa el fluxe de disseny dâaquesta tecnologia a travĂ©s del prototipat de varies aplicacions dâenginyeria (sistemes de control, coprocessadors aritmĂštics, processadors dâimatge, etc.), demostrant un nivell de maduresa viable ja per a la seva explotaciĂł a la indĂșstria
Efficient implementation of channel estimation algorithm for beamforming
Abstract. The future 5G mobile network technology is expected to offer significantly better performance than its predecessors. Improved data rates in conjunction with low latency is believed to enable technological revolutions such as self-driving cars. To achieve faster data rates, MIMO systems can be utilized. These systems enable the use of spatial filtering technique known as beamforming. Beamforming that is based on the preacquired channel matrix is computationally very demanding causing challenges in achieving low latency. By acquiring the channel matrix as efficiently as possible, we can facilitate this challenge.
In this thesis we examined the implementation of channel estimation algorithm for beamforming with a digital signal processor specialized in vector computation. We present implementations for different antenna configurations based on three different approaches. The results show that the best performance is achieved by applying the algorithm according to the limitations given by the system and the processor architecture. Although the exploitation of the parallel architecture was proved to be challenging, the implementation of the algorithm would have benefitted from the greater amount of parallelism. The current parallel resources will be a challenge especially in the future as the size of antenna configurations is expected to grow.Keilanmuodostuksen tarvitseman kanavaestimointialgoritmin tehokas toteutus. TiivistelmÀ. Tulevan viidennen sukupolven mobiiliverkkoteknologian odotetaan tarjoavan merkittÀvÀsti edeltÀjÀÀnsÀ parempaa suorituskykyÀ. TÀmÀn suorituskyvyn tarjoamat suuret datanopeudet yhdistettynÀ pieneen latenssiin uskotaan mahdollistavan esimerkiksi itsestÀÀn ajavat autot. Suurempien datanopeuksien saavuttamiseksi voidaan hyödyntÀÀ monitiekanavassa kÀytettÀvÀÀ MIMO-systeemiÀ, joka mahdollistaa keilanmuodostuksena tunnetun spatiaalisen suodatusmenetelmÀn kÀytön. EtukÀteen hankittuun kanavatilatietoon perustuva keilanmuodostus on laskennallisesti erittÀin kallista. TÀmÀ aiheuttaa haasteita verkon pienen latenssivaatimuksen saavuttamisessa.
TÀssÀ työssÀ tutkittiin keilanmuodostukselle tarkoitetun kanavaestimointialgoritmin tehokasta toteutusta hyödyntÀen vektorilaskentaan erikoistunutta prosessoriarkkitehtuuria. TyössÀ esitellÀÀn kolmea eri lÀhestymistapaa hyödyntÀvÀt toteutukset eri kokoisille antennikonfiguraatioille. Tuloksista nÀhdÀÀn, ettÀ paras suorituskyky saavutetaan sovittamalla algoritmi jÀrjestelmÀn ja arkkitehtuurin asettamien rajoitusten mukaisesti. Vaikka rinnakkaisarkkitehtuurin hyödyntÀminen asetti omat haasteensa, olisi algoritmin toteutus hyötynyt suuremmasta rinnakkaisuuden mÀÀrÀstÀ. Nykyinen rinnakkaisuuden mÀÀrÀ tulee olemaan haaste erityisesti tulevaisuudessa, sillÀ antennikonfiguraatioiden koon odotetaan kasvavan
Analog Signal Buffering and Reconstruction
Wireless sensor networks (WSNs) are capable of a myriad of tasks, from monitoring critical infrastructure such as bridges to monitoring a person\u27s vital signs in biomedical applications. However, their deployment is impractical for many applications due to their limited power budget. Sleep states are one method used to conserve power in resource-constrained systems, but they necessitate a wake-up circuit for detecting unpredictable events. In conventional wake-up-based systems, all information preceding a wake-up event will be forfeited. To avoid this data loss, it is necessary to include a buffer that can record prelude information without sacrificing the power savings garnered by the active use of sleep states.;Unfortunately, traditional memory buffer systems utilize digital electronics which are costly in terms of power. Instead of operating in the target signal\u27s native analog environment, a digital buffer must first expend a great deal of energy to convert the signal into a digital signal. This issue is further compounded by the use of traditional Nyquist sampling which does not adapt to the characteristics of a dynamically changing signal. These characteristics reveal why a digital buffer is not an appropriate choice for a WSN or other resource-constrained system.;This thesis documents the development of an analog pre-processing block that buffers an incoming signal using a new method of sampling. This method requires sampling only local maxima and minima (both amplitude and time), effectively approximating the instantaneous Nyquist rate throughout a time-varying signal. The use of this sampling method along with ultra-low-power analog electronics enables the entire system to operate in the muW power levels. In addition to these power saving techniques, a reconfigurable architecture will be explored as infrastructure for this system. This reconfigurable architecture will also be leveraged to explore wake-up circuits that can be used in parallel with the buffer system
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