9 research outputs found

    Generalizations of tournaments: A survey

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    A new framework for analysis of coevolutionary systems:Directed graph representation and random walks

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    Studying coevolutionary systems in the context of simplified models (i.e. games with pairwise interactions between coevolving solutions modelled as self plays) remains an open challenge since the rich underlying structures associated with pairwise comparison-based fitness measures are often not taken fully into account. Although cyclic dynamics have been demonstrated in several contexts (such as intransitivity in coevolutionary problems), there is no complete characterization of cycle structures and their effects on coevolutionary search. We develop a new framework to address this issue. At the core of our approach is the directed graph (digraph) representation of coevolutionary problem that fully captures structures in the relations between candidate solutions. Coevolutionary processes are modelled as a specific type of Markov chains ? random walks on digraphs. Using this framework, we show that coevolutionary problems admit a qualitative characterization: a coevolutionary problem is either solvable (there is a subset of solutions that dominates the remaining candidate solutions) or not. This has an implication on coevolutionary search. We further develop our framework that provide the means to construct quantitative tools for analysis of coevolutionary processes and demonstrate their applications through case studies. We show that coevolution of solvable problems corresponds to an absorbing Markov chain for which we can compute the expected hitting time of the absorbing class. Otherwise, coevolution will cycle indefinitely and the quantity of interest will be the limiting invariant distribution of the Markov chain. We also provide an index for characterizing complexity in coevolutionary problems and show how they can be generated in a controlled mannerauthorsversionPeer reviewe

    Sets as graphs

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    The aim of this thesis is a mutual transfer of computational and structural results and techniques between sets and graphs. We study combinatorial enumeration of sets, canonical encodings, random generation, digraph immersions. We also investigate the underlying structure of sets in algorithmic terms, or in connection with hereditary graphs classes. Finally, we employ a set-based proof-checker to verify two classical results on claw-free graph

    Arc Reversals in Tournaments.

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    A study on Dicycles and Eulerian Subdigraphs

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    1. Dicycle cover of Hamiltonian oriented graphs. A dicycle cover of a digraph D is a family F of dicycles of D such that each arc of D lies in at least one dicycle in F. We investigate the problem of determining the upper bounds for the minimum number of dicycles which cover all arcs in a strong digraph. Best possible upper bounds of dicycle covers are obtained in a number of classes of digraphs, including strong tournaments, Hamiltonian oriented graphs, Hamiltonian oriented complete bipartite graphs, and families of possibly non-hamiltonian digraphs obtained from these digraphs via a sequence of 2-sum operations.;2. Supereulerian digraphs with given local structures . Catlin in 1988 indicated that there exist graph families F such that if every edge e in a graph G lies in a subgraph He of G isomorphic to a member in F, then G is supereulerian. In particular, if every edge of a connected graph G lies in a 3-cycle, then G is supereulerian. The purpose of this research is to investigate how Catlin\u27s theorem can be extended to digraphs. A strong digraph D is supereulerian if D contains a spanning eulerian subdigraph. We show that there exists an infinite family of non-supereulerian strong digraphs each arc of which lies in a directed 3-cycle. We also show that there exist digraph families H such that a strong digraph D is supereulerian if every arc a of D lies in a subdigraph Ha isomorphic to a member of H. A digraph D is symmetric if (x, y) ∈ A( D) implies (y, x) ∈ A( D); and is symmetrically connected if every pair of vertices of D are joined by a symmetric dipath. A digraph D is partially symmetric if the digraph obtained from D by contracting all symmetrically connected components is symmetrically connected. It is known that a partially symmetric digraph may not be symmetrically connected. We show that symmetrically connected digraphs and partially symmetric digraphs are such families. Sharpness of these results are discussed.;3. On a class of supereulerian digraphs. The 2-sum of two digraphs D1 and D2, denoted D1 ⊕2 D2, is the digraph obtained from the disjoint union of D 1 and D2 by identifying an arc in D1 with an arc in D2. A digraph D is supereulerian if D contains a spanning eulerian subdigraph. It has been noted that the 2-sum of two supereulerian (or even hamiltonian) digraphs may not be supereulerian. We obtain several sufficient conditions on D1 and D 2 for D1 ⊕2 D 2 to be supereulerian. In particular, we show that if D 1 and D2 are symmetrically connected or partially symmetric, then D1 ⊕2 D2 is supereulerian

    Subject Index Volumes 1–200

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    Design of robust asynchronous reconfigurable controllers for parallel synchronization using embedded graphs

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    PhD Thesis: This is a revised version received 24/5/16. The definitive version is the print copy in the Research Reserve Collection of the University LibrarySynchronization is a key System-on-Chip (SoC) design issue in modern technologies. As the number of operating points under consideration increases, specifications which are capable of altering key parameters such as the time available for synchronization and Mean Time Between Failures (MTBF) in response to input from the user/system become desirable. This thesis explores how a combination of parallelism and scheduling, referred to as wagging, can be utilized to construct schedulers for synchronizer designs which are capable of pooling the gain-bandwidth products of their composite devices, in order to satisfy this requirement. In this work, we explore the ways in which the areas of graph theory and reconfigurable hardware design can be applied to generate both combinational and sequential scheduler designs, which satisfy the behavior requirement above. Further to this point, this work illustrates that such a scheduler is primarily comprised of an interrupt subsystem, and a reconfigurable token ring. This thesis explores how both of these components can be controlled in absence of a clock signal, as well as the design challenges inherent to each part. The final noteworthy issue in this study is with regard to the flow control of data in a parallel synchronizer that incorporates a First-In First-Out (FIFO) buffer to decouple the reading and writing operations from each other. Such a structure incurs penalties if the data rates on both sides are not well matched. This work presents a method by which combinations of serial and parallel reading operations are used to minimize this mismatch

    EUROCOMB 21 Book of extended abstracts

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