1,066 research outputs found

    Statistical Power Supply Dynamic Noise Prediction in Hierarchical Power Grid and Package Networks

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    One of the most crucial high performance systems-on-chip design challenge is to front their power supply noise sufferance due to high frequencies, huge number of functional blocks and technology scaling down. Marking a difference from traditional post physical-design static voltage drop analysis, /a priori dynamic voltage drop/evaluation is the focus of this work. It takes into account transient currents and on-chip and package /RLC/ parasitics while exploring the power grid design solution space: Design countermeasures can be thus early defined and long post physical-design verification cycles can be shortened. As shown by an extensive set of results, a carefully extracted and modular grid library assures realistic evaluation of parasitics impact on noise and facilitates the power network construction; furthermore statistical analysis guarantees a correct current envelope evaluation and Spice simulations endorse reliable result

    Voltage controlled oscillator for mm-wave radio systems

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    Abstract. The advancement in silicon technology has accelerated the development of integrated millimeter-wave transceiver systems operating up to 100 GHz with sophisticated functionality at a reduced consumer cost. Due to the progress in the field of signal processing, frequency modulated continuous wave (FMCW) radar has become common in recent years. A high-performance local oscillator (LO) is required to generate reference signals utilized in these millimeter-wave radar transceivers. To accomplish this, novel design techniques in fundamental voltage controlled oscillators (VCO) are necessary to achieve low phase noise, wide frequency tuning range, and good power efficiency. Although integrated VCOs have been studied for decades, as we move higher in the radio frequency spectrum, there are new trade-offs in the performance parameters that require further characterization. The work described in this thesis aims to design a fully integrated fundamental VCO targeting to 150 GHz, i.e., D-Band. The purpose is to observe and analyze the design limitations at these high frequencies and their corresponding trade-offs during the design procedure. The topology selected for this study is the cross-coupled LC tank VCO. For the study, two design topologies were considered: a conventional cross-coupled LC tank VCO and an inductive divider cross-coupled LC tank VCO. The conventional LC tank VCO yields better performance in terms of phase noise and tuning range. It is observed that the VCO is highly sensitive to parasitic contributions by the transistors, and the layout interconnects, thus limiting the targeted frequency range. The dimensions of the LC tank and the transistors are selected carefully. Moreover, the VCO performance is limited by the low Q factor of the LC tank governed by the varactor that is degrading the phase noise performance and the tuning range, respectively. The output buffer loaded capacitance and the core power consumption of the VCO are optimized. The layout is drawn carefully with strategies to minimize the parasitic effects. Considering all the design challenges, a 126 GHz VCO with a tuning range of 3.9% is designed. It achieves FOMT (Figure-of-merit) of -172 dBc/Hz, and phase noise of -99.14 dBc/Hz at 10 MHz offset, Core power consumption is 8.9 mW from a 1.2 V supply. Just falling short of the targeted frequency, the design is suitable for FMCW radar applications for future technologies. The design was done using Silicon-on-Insulator (SOI) CMOS technology

    UHF Power Transmission for Passive Sensor Transponders

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    Passive transponder tags operating in the ultra high frequency (UHF) range receive their power supply from the electromagnetic carrier wave from a remote base station. The maximum range is largely determined by the circuits’ current consumption and the rectifier efficiency. Reading ranges of several meters have recently been reported for several state of the art RFID (Radio frequency IDentification) tags [1]. The presented UHF transponder chip with integrated temperature sensor was designed for a 0.35 ?m CMOS process with EEPROM, Schottky diodes, and double poly layers. Due to a more complex architecture and additional functionality, the power consumption of the presented sensor transponder tag is significantly larger than that of simple RFID tags. The A/D conversion requires a stable, ripple-free supply voltage with a relatively large DC value. A novel rectifier circuit generates the supply voltage from the high frequency antenna signal. The circuit requires only -11.4 dBm input power and is insensitive to temperature and process variations. The maximum operating distance is approximately 4.5 m

    Ultra-compact (80 mm2) differential-mode ultra-wideband (UWB) bandpass filters with common-mode noise suppression

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    This paper presents a novel approach for the implementation of balanced ultra-wideband (UWB) bandpass filters with common-mode noise suppression. To a first-order approximation, the differential-mode filter response is described by the canonical circuit model of a bandpass filter, i.e., a cascade of series-connected resonators alternating with shunt-connected parallel resonant tanks. Thus, the series branches of the balanced filter are implemented by means of inductive strips and patch capacitors, whereas the shunt sections are realized through mirrored stepped-impedance resonators (SIRs) and low-impedance (i.e., capacitive) short transmission-line sections. For the differential mode, the symmetry plane is a virtual ground, the wide strip sections of the SIRs are effectively grounded, and the SIRs behave as grounded inductors parallel connected to capacitors. However, for the common mode, where the symmetry plane is an open (magnetic wall), the SIRs act as shunt-connected series resonators, thus providing transmission zeros at their resonance frequencies. By properly tailoring the location of these transmission zeros, rejection of the common mode over the differential filter passband can be achieved. To illustrate the potential of the approach, an order-5 balanced bandpass filter covering the regulated band for UWB communications (3.1-10.6 GHz) is designed and fabricated. The filter exhibits common-mode rejection above 10 dB over the whole differential filter passband, with differential-mode insertion losses lower than 1.9 dB and return losses better than 10 dB. Since the proposed design approach is based on planar semi-lumped components, filter size is as small as 10.5 mm X 7.6 m

    Automated Design of Common-Mode Suppressed Balanced Wideband Bandpass Filters by Means of Aggressive Space Mapping

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    The automated and unattended design of balanced microstrip wideband bandpass filters by means of aggressive space mapping (ASM) optimization is reported in this paper. The proposed filters are based on multisection mirrored stepped impedance resonators (SIRs) coupled through quarter-wavelength transmission lines, acting as admittance inverters.This work was supported by MINECO-Spain (projects TEC2013-47037-C5-1-R, TEC2013-40600-R, TEC2013-49221-EXP), Generalitat de Catalunya (project 2014SGR-157), Institucio Catalana de Recerca i Estudis Avancats (who awarded Ferran Martin), and by FEDER funds.Sans, M.; Selga, J.; Velez, P.; Rodriguez Perez, AM.; Bonache Albacete, J.; Boria Esbert, VE.; Martin, F. (2015). Automated Design of Common-Mode Suppressed Balanced Wideband Bandpass Filters by Means of Aggressive Space Mapping. IEEE Transactions on Microwave Theory and Techniques. 63(12):3896-3908. https://doi.org/10.1109/TMTT.2015.2495180S38963908631

    Evaluation and implementation of a 5-level hybrid DC-DC converter

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    In this work, a hybrid voltage regulator topology is analyzed, implemented, and evaluated. The common topologies of DC-DC converters have proven to be lacking in some aspects, such as integrability for buck converters, or maximum efficiency for switched-capacitor regulators. The hybrid topology tackles these shortcomings by combining the advantages of switched-capacitor and inductor-based voltage regulators. A 5-level buck converter is evaluated, implemented, and compared to other converter implementations using the same components. The 5-Level Buck converter can achieve 5 different levels, allowing it to cover 4 operation regions, each between 2 levels. Accordingly, it covers a wide range of output voltages. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductor compared to both 3-level and conventional buck converters which makes it cheaper, smaller in size, and much more efficient. Simulations show proper functionality of the 5-Level topology, while putting restrictions on the inductor size, efficiency, and component footprint (or total converter area). A test PCB is implemented for verification of the functionality and experimental measurements show that for the same switching frequency and inductor size, the 5-level buck converter achieves up to 15% efficiency improvement over a conventional buck converter and a 3-level buck converter at certain output voltage ranges. Peak efficiency of 94% has been achieved by the 5-Level hybrid converter, which includes all external switching and conduction losses. The proposed hybrid topology proved to yield high conversion efficiency even in the face of component size limitations, which indicates potential benefit in using multilevel converters for several off-chip as well as on-chip applications

    Automated design of balanced wideband bandpass filters based on mirrored stepped impedance resonators (SIRs) and interdigital capacitors

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    This paper presents small balanced bandpass filters exhibiting wide differential-mode pass bands and high common-mode suppression. The filters are implemented in microstrip technology and their topology consists of multisection mirrored stepped impedance resonators (SIRs) alternating with mirrored interdigital capacitors. The mirrored SIRs provide the required common-mode transmission zeros to achieve effective rejection of that mode in the region of interest, i.e. the differential-mode pass band. An automated design method for such filters, based on aggressive space mapping, is reported. The method uses the equivalent circuit model of both the mirrored SIRs and the interdigital capacitors, and filter synthesis is based on a quasi-Newton iterative algorithm where parameter extraction is the key aspect. The automated design approach is illustrated through an order-3 filter, where it is demonstrated that the filter topology is generated from the specifications. As compared with previous balanced filters based on mirrored SIRs coupled through admittance inverters, the proposed filters of this work are smaller and the design method is simplified, since bandwidth compensation due to the narrowband functionality of the inverters is avoided.This work was supported by MINECO-Spain (projects no. TEC2013-47037-C5-1-R, TEC2013-40600-R, and TEC2013-49221-EXP), Generalitat de Catalunya (project no. 2014SGR-157), and Institucio Catalana de Recerca i Estudis Avancats (who has awarded Ferran Martin).Sans, M.; Selga, J.; Vélez, P.; Rodriguez Perez, AM.; Bonache, J.; Boria Esbert, VE.; Martin, F. (2016). Automated design of balanced wideband bandpass filters based on mirrored stepped impedance resonators (SIRs) and interdigital capacitors. International Journal of Microwave and Wireless Technologies. 8(4-5):731-740. https://doi.org/10.1017/S1759078716000672S73174084-

    Design and Control of Power Converters for High Power-Quality Interface with Utility and Aviation Grids

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    Power electronics as a subject integrating power devices, electric and electronic circuits, control, and thermal and mechanic design, requires not only knowledge and engineering insight for each subarea, but also understanding of interface issues when incorporating these different areas into high performance converter design.Addressing these fundamental questions, the dissertation studies design and control issues in three types of power converters applied in low-frequency high-power transmission, medium-frequency converter emulated grid, and high-frequency high-density aviation grid, respectively, with the focus on discovering, understanding, and mitigating interface issues to improve power quality and converter performance, and to reduce the noise emission.For hybrid ac/dc power transmission,• Analyze the interface transformer saturation issue between ac and dc power flow under line unbalances.• Proposed both passive transformer design and active hybrid-line-impedance-conditioner to suppress this issue.For transmission line emulator,• Propose general transmission line emulation schemes with extension capability.• Analyze and actively suppress the effects of sensing/sampling bias and PWM ripple on emulation considering interfaced grid impedance.• Analyze the stability issue caused by interaction of the emulator and its interfaced impedance. A criterion that determines the stability and impedance boundary of the emulator is proposed.For aircraft battery charger,• Investigate architectures for dual-input and dual-output battery charger, and a three-level integrated topology using GaN devices is proposed to achieve high density.• Identify and analyze the mechanisms and impacts of high switching frequency, di/dt, dv/dt on sensing and power quality control; mitigate solutions are proposed.• Model and compensate the distortion due to charging transition of device junction capacitances in three-level converters.• Find the previously overlooked device junction capacitance of the nonactive devices in three-level converters, and analyze the impacts on switching loss, device stress, and current distortion. A loss calculation method is proposed using the data from the conventional double pulse tester.• Establish fundamental knowledge on performance degradation of EMI filters. The impacts and mechanisms of both inductive and capacitive coupling on different filter structures are understood. Characterization methodology including measuring, modeling, and prediction of filter insertion loss is proposed. Mitigation solutions are proposed to reduce inter-component coupling and self-parasitics

    Designing of Low Power RF-Receiver Front-end with CMOS Technology

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    This thesis studies how to design ultra low power radio-receiver front-end circuit consisting of a low-noise CMOS amplifier and mixer for low power Bluetooth applications. This system is designed in 65-nm CMOS technology with the voltage source of 1.2 V, and it operates at 2.4 GHz. This research project includes the design of radio frequency integrated circuit with CMOS technology using CAD software for circuit design, layout design, pre and post-layout simulations. Firstly, brief study about both Low noise amplifier (LNA) and mixer has been done, and then the design structure such as, input matching network of LNA, noise of system, gain and linearity have been discussed. Later, next section reports simulation results of LNA, mixer and eventually their combination. Furthermore, the effect of packaging and non-ideal on-chip circuit performance has been considered and shown in comparison tables for more clarity. Finally, after the layout design, the obtained results of both post-layout and pre-layout simulations are compared and shown the stability of the design with parasitics consideration

    Design, Fault Modeling and Testing Of a Fully Integrated Low Noise Amplifier (LNA) in 45 nm CMOS Technology for Inter and Intra-Chip Wireless Interconnects

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    Research in recent years has demonstrated that intra and inter-chip wireless interconnects are capable of establishing energy-efficient data communications within as well as between multiple chips. This thesis introduces a circuit level design of a source degenerated two stage common source low noise amplifier suitable for such wireless interconnects in 45-nm CMOS process. The design consists of a simple two-stage common source structure based Low Noise Amplifier (LNA) to boost the degraded received signal. Operating at 60GHz, the proposed low noise amplifier consumes only 4.88 mW active power from a 1V supply while providing 17.2 dB of maximum gain at 60 GHz operating frequency at very low noise figure of 2.8 dB, which translates to a figure of merit of 16.1 GHz and IIP3 as -14.38 dBm
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