Integrated CMOS Energy Harvesting Converter with Digital Maximum Power Point Tracking for a Portable Thermophotovoltaic Power Generator

This paper presents an integrated maximum power point tracking system for use with a thermophotovoltaic (TPV) portable power generator. The design, implemented in 0.35 μm CMOS technology, consists of a low-power control stage and a dc-dc boost power stage with soft-switching capability. With a nominal input voltage of 1 V, and an output voltage of 4 V, we demonstrate a peak conversion efficiency under nominal conditions of over 94% (overall peak efficiency over 95%), at a power level of 300 mW. The control stage uses lossless current sensing together with a custom low-power time-based ADC to minimize control losses. The converter employs a fully integrated digital implementation of a peak power tracking algorithm, and achieves a measured tracking efficiency above 98%. A detailed study of achievable efficiency versus inductor size is also presented, with calculated and measured results.Interconnect Focus Center (United States. Defense Advanced Research Projects Agency and Semiconductor Research Corporation

Analyses and design strategies for fundamental enabling building blocks: Dynamic comparators, voltage references and on-die temperature sensors

Dynamic comparators and voltage references are among the most widely used fundamental building blocks for various types of circuits and systems, such as data converters, PLLs, switching regulators, memories, and CPUs. As thermal constraints quickly emerged as a dominant performance limiter, on-die temperature sensors will be critical to the reliable operation of future integrated circuits. This dissertation investigates characteristics of these three enabling circuits and design strategies for improving their performances. One of the most critical specifications of a dynamic comparator is its input referred offset voltage, which is pivotal to achieving overall system performance requirements of many mixed-signal circuits and systems. Unlike offset voltages in other circuits such as amplifiers, the offset voltage in a dynamic comparator is extremely challenging to analyze and predict analytically due to its dependence on transient response and due to internal positive feedback and time-varying operating points in the comparator. In this work, a novel balanced method is proposed to facilitate the evaluation of time-varying operating points of transistors in a dynamic comparator. Two types of offsets are studied in the model: (1) static offset voltage caused by mismatches in mobilities, transistor sizes, and threshold voltages, and (2) dynamic offset voltage caused by mismatches in parasitic capacitors or loading capacitors. To validate the proposed method, dynamic comparators in two prevalent topologies are implemented in 0.25 μm and 40 nm CMOS technologies. Agreement between predicted results and simulated results verifies the effectiveness of the proposed method. The new method and the analytical models enable designers to identify the most dominant contributors to offset and to optimize the dynamic comparators\u27 performances. As an illustrating example, the Lewis-Gray dynamic comparator was analyzed using the balanced method and redesigned to minimize its offset voltage. Simulation results show that the offset voltage was easily reduced by 41% while maintaining the same silicon area. A bandgap voltage reference is one of the core functional blocks in both analog and digital systems. Despite the reported improvements in performance of voltage references, little attention has been focused on theoretical characterizations of non-ideal effects on the value of the output voltage, on the inflection point location and on the curvature of the reference voltage. In this work, a systematic approach is proposed to analytically determine the effects of two non-ideal elements: the temperature dependent gain-determining resistors and the amplifier offset voltage. The effectiveness of the analytical models is validated by comparing analytical results against Spectre simulation results. Research on on-die temperature sensor design has received rapidly increasing attention since component and power density induced thermal stress has become a critical factor in the reliable operation of integrated circuits. For effective power and thermal management of future multi-core systems, hundreds of sensors with sufficient accuracy, small area and low power are required on a single chip. This work introduces a new family of highly linear on chip temperature sensors. The proposed family of temperature sensors expresses CMOS threshold voltage as an output. The sensor output is independent of power supply voltage and independent of mobility values. It can achieve very high temperature linearity, with maximum nonlinearity around +/- 0.05oC over a temperature range of -20oC to 100oC. A sizing strategy based on combined analytical analysis and numerical optimization has been presented. Following this method, three circuits A, B and C have been designed in standard 0.18 ym CMOS technology, all achieving excellent linearity as demonstrated by Cadence Spectre simulations. Circuits B and C are the modified versions of circuit A, and have improved performance at the worst corner-low voltage supply and high threshold voltage corner. Finally, a direct temperature-to-digital converter architecture is proposed as a master-slave hybrid temperature-to-digital converter. It does not require any traditional constant reference voltage or reference current, it does not attempt to make any node voltage or branch current constant or precisely linear to temperature, yet it generates a digital output code that is very linear with temperature

Power Converters in Power Electronics

In recent years, power converters have played an important role in power electronics technology for different applications, such as renewable energy systems, electric vehicles, pulsed power generation, and biomedical sciences. Power converters, in the realm of power electronics, are becoming essential for generating electrical power energy in various ways. This Special Issue focuses on the development of novel power converter topologies in power electronics. The topics of interest include, but are not limited to: Z-source converters; multilevel power converter topologies; switched-capacitor-based power converters; power converters for battery management systems; power converters in wireless power transfer techniques; the reliability of power conversion systems; and modulation techniques for advanced power converters