Automatic synthesis of analog layout : a survey

A review of recent research in the automatic synthesis of physical geometry for analog integrated circuits is presented. On introduction, an explanation of the difficulties involved in analog layout as opposed to digital layout is covered. Review of the literature then follows. Emphasis is placed on the exposition of general methods for addressing problems specific to analog layout, with the details of specific systems only being given when they surve to illustrate these methods well. The conclusion discusses problems remaining and offers a prediction as to how technology will evolve to solve them. It is argued that although progress has been and will continue to be made in the automation of analog IC layout, due to fundamental differences in the nature of analog IC design as opposed to digital design, it should not be expected that the level of automation of the former will reach that of the latter any time soon

Low power CMOS analog multipliers.

CMOS analog multiplier is a very important building block and programming element in analog signal processing. Although high-performance multipliers using bipolar transistors have been available for 40 years, CMOS multiplier implementation is still a challenging subject especially for low-power and low-noise circuit design. Since the supply voltage is normally fixed for analog multiplier structures, we use the total current to represent the power dissipation. Our basic idea for low power design of analog multipliers is to fit most of the transistors into the linear region, while at the same time keeping the drain-to-source voltage as low as possible to decease the drain current. And also, we use PMOS transistors for the devices working in the saturation region to further decrease the drain current and improve the linearity performance. Two low power CMOS analog multiplier designs have been proposed in this thesis. We gave detailed performance analysis and some design considerations for these structures. Cadence Hspice simulation verified our analysis. To ensure a fair comparison, we also simulated the performance of a previous multiplier structure, which was considered to be one of the best multiplier structures with low power and low noise performance. Extensive experiments and comparison for these structures show that the proposed CMOS analog multipliers have much less power dissipation than that of previous structures, while at the same time, satisfying other performance requirements. The proposed analog multipliers would be good choices in the applications where low power dissipation is an important consideration.Dept. of Electrical and Computer Engineering. Paper copy at Leddy Library: Theses & Major Papers - Basement, West Bldg. / Call Number: Thesis2004 .L5. Source: Masters Abstracts International, Volume: 43-01, page: 0280. Adviser: Chunhong Chen. Thesis (M.A.Sc.)--University of Windsor (Canada), 2004

Confession Session: Learning from Others Mistakes

Accepted versio

A Novel Multifunction Digital Chip Design Based on CMOS Technology

The realization of an analog-to-digital-conversion chip has great significance in the applications of electronic products. By considering mature time–number digitization, a new multifunction digital chip with a long time delay was designed in this study on the basis of the principle of analog-to-time conversion (ATC) and the realization of long time delay. With additional resistance, capacitance, and transistors, this chip can easily realize ATC, monostable triggers, Schmitt triggers, and multivibrators. The circuit composition of this chip was analyzed, and every module design was introduced. According to the simulation result of Hspice and CSMC 2P2M CMOS (Complementary Metal Oxide Semiconductor) process database, the chip layout (1mm2) design was accomplished by using CSMC 2P2M CMOS technology. Finally, the designed chip was applied in multiproject wafer flow. The flow test demonstrated that this new chip can meet design goal and is applicable to various digital integrated chip designs as an IP (intellectual property) core

Design and Assembly of High-Temperature Signal Conditioning System on LTCC with Silicon Carbide CMOS Circuits

The objective of the work described in this dissertation paper is to develop a prototype electronic module on a low-temperature co-fired ceramic (LTCC) material. The electronic module would perform signal conditioning of sensor signals (thermocouples) operating under extreme conditions for applications like gas turbines to collect data on the health of the turbine blades during operation so that the turbines do not require shutdown for inspection to determine if maintenance is required. The collected data can indicate when such shutdowns, which cost $1M per day, should be scheduled and maintenance actually performed. The circuits for the signal conditioning system within the prototype module must survive the extreme temperature, pressure, and centrifugal force, or G-force, present in these settings. Multiple fabrication runs on different integrated silicon carbide (SiC) process technologies have been carried out to meet the system requirements. The key circuits described in this dissertation are - two-stage op amp topologies and voltage reference, which are designed and fabricated in a new SiC CMOS process. The SiC two-stage op amp with PFET differential input pair showed 48.9 dB of DC gain at 500oC. The voltage reference is the first in SiC CMOS technology to employ an op amp-based topology. The op amp circuit in the voltage reference is a two-stage with NFET differential input pair that uses the indirect compensation technique for the first time in the SiC CMOS process to provide 42.5 dB gain at 350oC. The designed prototype module implemented with these circuits was verified to provide signal conditioning and signal transmission at 300oC. The signal transmission circuit on the module was also verified to operate with a resonant inductive wireless power transfer method at a frequency of 11.8 MHz for the first time. A second prototype module was also developed with the previously fabricated 1.2 µm SiC CMOS process. The second module was successfully tested (with wired power supply) to operate at 440oC inside a probe-station and also verified for the first time to sustain signal transmission (34.65 MHz) capability inside a spin-rig at a rotational speed of 10,920 rpm. All designed modules have dimensions of (length) 68.5 mm by (width) 34.3 mm to conform to the physical size requirements of the gas turbine blade

System-level design and RF front-end implementation for a 3-10ghz multiband-ofdm ultrawideband receiver and built-in testing techniques for analog and rf integrated circuits

This work consists of two main parts: a) Design of a 3-10GHz UltraWideBand (UWB) Receiver and b) Built-In Testing Techniques (BIT) for Analog and RF circuits. The MultiBand OFDM (MB-OFDM) proposal for UWB communications has received significant attention for the implementation of very high data rate (up to 480Mb/s) wireless devices. A wideband LNA with a tunable notch filter, a downconversion quadrature mixer, and the overall radio system-level design are proposed for an 11-band 3.4-10.3GHz direct conversion receiver for MB-OFDM UWB implemented in a 0.25mm BiCMOS process. The packaged IC includes an RF front-end with interference rejection at 5.25GHz, a frequency synthesizer generating 11 carrier tones in quadrature with fast hopping, and a linear phase baseband section with 42dB of gain programmability. The receiver IC mounted on a FR-4 substrate provides a maximum gain of 67-78dB and NF of 5-10dB across all bands while consuming 114mA from a 2.5V supply. Two BIT techniques for analog and RF circuits are developed. The goal is to reduce the test cost by reducing the use of analog instrumentation. An integrated frequency response characterization system with a digital interface is proposed to test the magnitude and phase responses at different nodes of an analog circuit. A complete prototype in CMOS 0.35mm technology employs only 0.3mm2 of area. Its operation is demonstrated by performing frequency response measurements in a range of 1 to 130MHz on 2 analog filters integrated on the same chip. A very compact CMOS RF RMS Detector and a methodology for its use in the built-in measurement of the gain and 1dB compression point of RF circuits are proposed to address the problem of on-chip testing at RF frequencies. The proposed device generates a DC voltage proportional to the RMS voltage amplitude of an RF signal. A design in CMOS 0.35mm technology presents and input capacitance <15fF and occupies and area of 0.03mm2. The application of these two techniques in combination with a loop-back test architecture significantly enhances the testability of a wireless transceiver system