Switched-capacitor silicon compiler

A switched-capacitor (SC) silicon compiler will be described in this report. The input to this system is a set of specifications and a circuit description of an SC block. It has an opamp synthesis tool which is based on the selection and assembly of primitive modules. The opamp circuit topology is formed by searching through a set of styles yielding high performance opamp circuits serving a wide range of SC network applications. The layout strategy and architecture are such that they eliminate any crossover of sensitive signals by insensitive signals; Thus avoiding any special routing algorithm for sensitive routing. The results is a compact, parasitic-insensitive and "standard cell" type layout of an SC block with user-defined height. All blocks are placed and routed together by a general auto-placement and router tool

A new design methodology for mixed level and mixed signal simulation using PSpice A/D and VHDL

PSpice A/D is a simulation package that is used to analyze and predict the performance of analog and mixed signal circuits. It is very popular especially among Printed Circuit Board (PCB) engineers to verify board level designs. However, PSpice A/D currently lacks the ability to simulate analog components connected to digital circuits that are modeled using Hardware Descriptive Languages (HDLs), such as VHDL and Verilog HDL. Simulation of HDL models in PSpice A/D is necessary to verify mixed signal PCBs where programmable logic devices like Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) are connected to discrete analog components. More than 60% of the PCBs that are designed today contain at least one FPGA or CPLD. This thesis investigates the possibility of simulating VHDL models in PSpice A/D. A new design methodology and the necessary tools to achieve this goal are presented. The new design methodology achieves total system verification at PCB level. Total system verification reduces design failures and hence increases reliability. It also allows reducing the overall time to market. A mixed signal design from NASA Goddard Space Flight Center for a brushless three phase motor that runs a space application is implemented by following the proposed design methodology

ToPoliNano: Nanoarchitectures Design Made Real

Many facts about emerging nanotechnologies are yet to be assessed. There are still major concerns, for instance, about maximum achievable device density, or about which architecture is best fit for a specific application. Growing complexity requires taking into account many aspects of technology, application and architecture at the same time. Researchers face problems that are not new per se, but are now subject to very different constraints, that need to be captured by design tools. Among the emerging nanotechnologies, two-dimensional nanowire based arrays represent promising nanostructures, especially for massively parallel computing architectures. Few attempts have been done, aimed at giving the possibility to explore architectural solutions, deriving information from extensive and reliable nanoarray characterization. Moreover, in the nanotechnology arena there is still not a clear winner, so it is important to be able to target different technologies, not to miss the next big thing. We present a tool, ToPoliNano, that enables such a multi-technological characterization in terms of logic behavior, power and timing performance, area and layout constraints, on the basis of specific technological and topological descriptions. This tool can aid the design process, beside providing a comprehensive simulation framework for DC and timing simulations, and detailed power analysis. Design and simulation results will be shown for nanoarray-based circuits. ToPoliNano is the first real design tool that tackles the top down design of a circuit based on emerging technologie

Implementation feasibility of an integrated LPDDR4 PHY block

One of the bottlenecks in the performance of academic RISC-V ASIC processors is high-speed memory access. The use of high speed DDR RAM chips on the board requires the integration in the ASIC of a very complex physical interface block (PHY) that encompasses analog and digital parts. This PHY block is thus technology-specific and very expensive to acquire. Recently, Wavious Ltd. published an open-source description of an LPDDR4x and LPDDR5 with an Apache license containing the digital part and wrappers for the analog parts. This master's thesis will start from this implementation, and will study the feasibility and cost of implementation of this IP for the Barcelona Supercomputing Center RISC-V processor initiative