Physics and technologies of silicon LDMOSFET for radio frequency applications

This thesis is devoted to the investigation of devices and technologies of Lateral Double-Diffused- Metal-Oxide-Semiconductor-Field-Effect-Transistor for Radio Frequency (RP) applications. Theoretical analysis and extensive 2-D process and device simulation results are presented. Theoretical analysis and simulations are carried out on RESURF LDMOS in both bulk and SOI substrate in terms of breakdown characteristics, transconductance, on resistance and CV characteristics. Quasi-saturation is a common phenomenon in DMOS devices. In this work, the dependence of quasi-saturation current on device physical and geometrical parameters is investigated in SOI RP LDMOS. Physical insight is gained into quasi-saturation on SOI RP LDMOS with different top silicon thickness and the same drift dose. It reveals that the difference in thick and thin film SOI lies in the different potential drop in the drift region. The influence of RESURF effect on quasi-saturation is also presented. It is shown that quasi-saturation current level can be affected by RESURF due to its influence on the drift dose. The mechanism of self-heating is presented and the influence of top silicon thickness, buried oxide thickness, voltage bias is studied through simulations. The change of peak temperature and its location with bias is due to the shift of electric field with voltage bias. A back-etch structure and fabrication process have been proposed to achieve a superior thermal performance. The negative differential conductance is not present in the non-isothermal IV curves. The temperature rise in the back-etch structure is less than 114 of that in the bulk structure. An RP LDMOS with a step drift doping profile on SIMOX substrate is evaluated. The fabrication process for the drift formation is proposed. The presented results demonstrate that step drift device has higher breakdown voltage than the conventional uniformly doped (UD) device, which provides the possibility to integrate LDMOS with low voltage CMOS for 28V base station application. This structure also has the advantage of suppressed kink effect due to the reduced electric field within the drift region. The step drift structure also features lower capacitance, improved drain current saturation behaviour and reduced self-heating at class AB bias point. For the first time, a novel sandwich structure for lateral RF MOSFET has been analysed based on silicon-on-nothing (SON) technology. The influence of device parameters on BV, CV and thermal performance has been investigated. Partial SON structure is found preferable in terms of heat conduct ability. Comparison on the electrical and thermal performance is made between SON LDMOSFET and conventional SOI alternative with BV of 40V. It is found that SON structure shows improvement in output capacitance and substrate loss. However, the temperature rise in SON device is higher compared to SOI alternative. The performance of the proposed sandwich SON structure has also been investigated in 28V base station applications, which requires breakdown voltage of 80V

Simulation of superjunction MOSFET devices

Master'sMASTER OF ENGINEERIN

High voltage 3-dimesional partial SOI technology platform for power integrated circuits

Partial SOI (PSOI) is a widely recognized technology suitable for High Voltage (HV) architectures for Power Integrated Circuits (PICs). Despite the added process complexity compared to SOI RESURF, this technology offers a wider range of voltage ratings due to the action of the depletion layer in the Handle Wafer (HW), reduced parasitic capacitances due to the extra volume of the depletion region in the HW and better heat conduction due to thinner buried oxide layer. The newly developed platform technology, featuring 3-dimensional designs to fully utilize the PSOI potential, is particularly relevant to the manufacturing of high voltage integrated circuits (HVICs) where low on-state resistance and reduced selfheating are essential requirements. This work presents a PSOI technology platform with voltage ratings ranging from 45 to 400V while providing low on-state resistance, good hot carrier injection stability as well as Electrostatic Discharge (ESD) capability of the HV devices. For example, for a 375V rated LDMOSFET, this technology achieves an on-state resistance of 1435mΩ.mm2 , an over 50% improvement compared to the state-of-the-art SOI technologies while maintaining competitive reliability

Design and fabrication of superjunction power MOSFET devices

Ph.DDOCTOR OF PHILOSOPH

A numerical study of partial-SOI LDMOSFETs

Abstract The high-voltage and self-heating behavior of partial-SOI (silicon-on-insulator) LDMOSFETs were studied numerically. Different locations of the silicon window were considered to investigate the electrical and thermal effects. It is found that the potential distribution of the partial-SOI LDMOSFET with the silicon window under the drain is similar to that of standard junction isolation devices. With the silicon window under the source the potential distribution is similar to that of the conventional SOI LDMOSFET. Using the two-dimensional numerical simulator MINIMOS-NT, we confirm that the breakdown voltage of partial-SOI LDMOSFETs with a silicon window under the source is higher than that of partial-SOI LDMOSFET with a silicon window under the drain

Optimisation of lateral super-junction multi-gate MOSFET for high drive current and low specific on-resistance in sub-100 V applications

The design and optimisation of a non-planar super-junction (SJ) Si MOSFET based on SOI technology for low voltage rating applications (below 100 V) is carried out with physically based commercial 3-D TCAD device simulations using Silvaco. We calibrate drift-diffusion simulations to experimental characteristics of the SJ multi-gate MOSFET (SJ-MGFET) aiming at improving drive current, breakdown voltage (BV), and specific on-resistance (Ron,sp). We investigate variations in the device architecture and improve device performance by optimizing doping profile under charge imbalance. The SJ-MGFET, using a folded alternating U-shaped n/p– SJ drift region pillar width of 0.3 μm with a trench depth of 2.7 μm achieves specific on-resistance (Ron,sp) of 0.21 mΩ.cm2 at a BV of 65 V. In comparison with conventional planar gate SJ-LDMOSFETs, the optimised SJ-MGFET gives 68% reduction in Ron,sp and 41% increase in a saturation drain current at a drain voltage of 5 V and a gate voltage of 10 V

Oxide bypassed power MOSFET devices

Master'sMASTER OF ENGINEERIN

Analysis of linear-doped Si/SiC power LDMOSFETs based on device simulation

This paper presents the design and optimization of a 600 V silicon-on-silicon carbide (Si/SiC) laterally diffused MOSFET with linear doping profile in the drift region for high-temperature applications. The proposed structure has an embedded silicon-on-insulator (SOI) layout through which the traditional graded doping theory for SOI can be applied in the Si/SiC architecture. An SOI counterpart is introduced as a benchmark and modeled alongside the proposed structure. Comparisons between them show that they have the near-identical OFF-state and breakdown characteristics, with a significant tunneling leakage component emerging above 450 V. In the ON state, the Si/SiC device has higher electrical resistance but much lower thermal resistance, leading to less self-heating and higher reliability

Optimization of power MOSFET devices suitable for integrated circuits

Táto doktorská práca sa zaoberá návrhom laterálnych výkonových tranzistorov s nízkym špecifickým odporom pri zapnutom stave, vhodných pre integráciu do Integrovaných Obvodov.This doctoral thesis deals with the design of lateral power transistor with lower specific on-resistance for integration into IC.The new model of MOSFET with waffle gate pattern is there described. For first, time the conformal transformation the Schwarz-Christoffel mapping has been used for the description of nonhomogeneous current distribution in the channel area of MOSFET with waffle gate pattern. In addition base on the figure of merit definition Area Increment (AI) the topological theoretical limit of MOSFET with waffle gate pattern has been a first time defined

High Performance Low Voltage Power Mosfet For High-frequency Synchronous Buck Converters

Power management solutions such as voltage regulator (VR) mandate DC-DC converters with high power density, high switching frequency and high efficiency to meet the needs of future computers and telecom equipment. The trend towards DC-DC converters with higher switching frequency presents significant challenges to power MOSFET technology. Optimization of the MOSFETs plays an important role in improving low-voltage DC-DC converter performance. This dissertation focuses on developing and optimizing high performance low voltage power MOSFETs for high frequency applications. With an inherently large gate charge, the trench MOSFET suffers significant switching power losses and cannot continue to provide sufficient performance in high frequency applications. Moreover, the influence of parasitic impedance introduced by device packaging and PCB assembly in board level power supply designs becomes more pronounced as the output voltage continues to decrease and the nominal current continues to increase. This eventually raises the need for highly integrated solutions such as power supply in package (PSiP) or on chip (PSoC). However, it is often more desirable in some PSiP architectures to reverse the source/drain electrodes from electrical and/or thermal point of view. In this dissertation, a stacked-die Power Block PSiP architecture is first introduced to enable DC-DC buck converters with a current rating up to 40 A and a switching frequency in the MHz range. New high- and low-side NexFETs are specially designed and optimized for the new PSiP architecture to maximize its efficiency and power density. In particular, a new NexFET structure with iv its source electrode on the bottom side of the die (source-down) is designed to enable the innovative stacked-die PSiP technology with significantly reduced parasitic inductance and package footprint. It is also observed that in synchronous buck converter very fast switching of power MOSFETs sometimes leads to high voltage oscillations at the phase node of the buck converter, which may introduce additional power loss and cause EMI related problems and undesirable electrical stress to the power MOSFET. At the same time, the synchronous MOSFET plays an important role in determining the performance of the synchronous buck converter. The reverse recovery of its body diode and the Cdv/dt induced false trigger-on are two major mechanisms that impact the performance of the SyncFET. This dissertation introduces a new approach to effectively overcome the aforementioned challenges associated with the state-of-art technology. The threshold voltage of the low-side NexFET is intentionally reduced to minimize the conduction and body diode related power losses. Meanwhile, a monolithically integrated gate voltage pull-down circuitry is proposed to overcome the possible Cdv/dt induced turn-on issue inadvertently induced by the low VTH SynFET. Through extensive modeling and simulation, all these innovative concepts are integrated together in a power module and fabricated with a 0.35µm process. With all these novel device technology improvements, the new power module delivers a significant improvement in efficiency and offers an excellent solution for future high frequency, high current density DC-DC converters. Megahertz operation of a Power v Block incorporating these new device techniques is demonstrated with an excellent efficiency observed