RF Power Amplifier and Its Envelope Tracking

This dissertation introduces an agile supply modulator with optimal transient performance for the envelope tracking supply in linear power amplifiers. For this purpose, an on-demand current source module, the bang-bang transient performance enhancer (BBTPE), is proposed. Its objective is to follow fast variations in input signals with reduced overshoot and settling time without deteriorating the steady-state performance of the buck regulator. The proposed approach enables fast system response through the BBTPE and an accurate steady-state output response through a low switching ripple and power efficient dynamic buck regulator. Fast output response with the help of the added module induces a slower rise of inductor current in the buck converter that further assists the proposed system to reduce both overshoot and settling time. To demonstrate the feasibility of the proposed solution, extensive simulations and experimental results from a discrete system are reported. The proposed supply modulator shows 80% improvement in rise time along with 60% reduction in both overshoot and settling time compared to the conventional dynamic buck regulator-based solution. Experimental results for a PA using the LTE 16-QAM 5 MHz standard shows improvement of 7.68 dB and 65.1% in ACPR and EVM, respectively. In a polar power amplifier, the input signal splits into phase and amplitude components using a non-linear conversion operation. This operation broadens the spectrum of the polar signal components. The information of amplitude and phase contains spectral images due to the sampling operation in non-linear conversion operation. These spectral images can be large and cause out-of-band emission in the output spectrum. In addition, during the recombination process of phase and amplitude, a delay mismatch between amplitude and phase signals, which can occur due to separate processing paths of amplitude and phase signals, causes out-of-band emissions, also known as spectral regrowth. This dissertation presents solutions to both of the issues of digital polar power amplifier: spectral images and delay mismatch. In order to reduce the problem of spectral images, interpolation of phase and amplitude is proposed in this work. This increases the effective sampling frequency of the amplitude and phase, which helps to improve the linearity by around 10 dB. In addition, a novel calibration scheme is proposed here for the delay mismatch between phase and amplitude path in a digital polar power amplifier. The scheme significantly reduces the spectral regrowth. The scheme uses the same path for phase and amplitude delay calculation after the recombination that allows having a robust calibration. Furthermore, it can be executed during the empty transmission slots. The proposed scheme is designed in a 40 nm CMOS technology and simulated with a 64-QAM IEEE 802.11n wireless standard. The scheme achieved 7.57 dB enhancement in ACLR and 84.35% improvement in EVM for a 3.5 ns mismatch in phase and amplitude path

Energy Efficient RF Transmitter Design using Enhanced Breakdown Voltage SOI-CMOS Compatible MESFETs

abstract: The high cut-off frequency of deep sub-micron CMOS technologies has enabled the integration of radio frequency (RF) transceivers with digital circuits. However, the challenging point is the integration of RF power amplifiers, mainly due to the low breakdown voltage of CMOS transistors. Silicon-on-insulator (SOI) metal semiconductor field effect transistors (MESFETs) have been introduced to remedy the limited headroom concern in CMOS technologies. The MESFETs presented in this thesis have been fabricated on different SOI-CMOS processes without making any change to the standard fabrication steps and offer 2-30 times higher breakdown voltage than the MOSFETs on the same process. This thesis explains the design steps of high efficiency and wideband RF transmitters using the proposed SOI-CMOS compatible MESFETs. This task involves DC and RF characterization of MESFET devices, along with providing a compact Spice model for simulation purposes. This thesis presents the design of several SOI-MESFET RF power amplifiers operating at 433, 900 and 1800 MHz with ~40% bandwidth. Measurement results show a peak power added efficiency (PAE) of 55% and a peak output power of 22.5 dBm. The RF-PAs were designed to operate in Class-AB mode to minimize the linearity degradation. Class-AB power amplifiers lead to poor power added efficiency, especially when fed with signals with high peak to average power ratio (PAPR) such as wideband code division multiple access (W-CDMA). Polar transmitters have been introduced to improve the efficiency of RF-PAs at backed-off powers. A MESFET based envelope tracking (ET) polar transmitter was designed and measured. A low drop-out voltage regulator (LDO) was used as the supply modulator of this polar transmitter. MESFETs are depletion mode devices; therefore, they can be configured in a source follower configuration to have better stability and higher bandwidth that MOSFET based LDOs. Measurement results show 350 MHz bandwidth while driving a 10 pF capacitive load. A novel polar transmitter is introduced in this thesis to alleviate some of the limitations associated with polar transmitters. The proposed architecture uses the backgate terminal of a partially depleted transistor on SOI process, which relaxes the bandwidth and efficiency requirements of the envelope amplifier in a polar transmitter. The measurement results of the proposed transmitter demonstrate more than three times PAE improvement at 6-dB backed-off output power, compared to the traditional RF transmitters.Dissertation/ThesisPh.D. Electrical Engineering 201

Highly efficient linear CMOS power amplifiers for wireless communications

The rapidly expanding wireless market requires low cost, high integration and high performance of wireless communication systems. CMOS technology provides benefits of cost effectiveness and higher levels of integration. However, the design of highly efficient linear CMOS power amplifier that meets the requirement of advanced communication standards is a challenging task because of the inherent difficulties in CMOS technology. The objective of this research is to realize PAs for wireless communication systems that overcoming the drawbacks of CMOS process, and to develop design approaches that satisfying the demands of the industry. In this dissertation, a cascode bias technique is proposed for improving linearity and reliability of the multi-stage cascode CMOS PA. In addition, to achieve load variation immunity characteristic and to enhance matching and stability, a fully-integrated balanced PA is implemented in a 0.18-m CMOS process. A triple-mode balanced PA using switched quadrature coupler is also proposed, and this work saved a large amount of quiescent current and further improved the efficiency in the back-off power. For the low losses and a high quality factor of passive output combining, a transformer-based quadrature coupler was implemented using integrated passive device (IPD) process. Various practical approaches for linear CMOS PA are suggested with the verified results, and they demonstrate the potential PA design approach for WCDMA applications using a standard CMOS technology.PhDCommittee Chair: Kenney, J. Stevenson; Committee Member: Jongman Kim; Committee Member: Kohl, Paul A.; Committee Member: Kornegay, Kevin T.; Committee Member: Lee, Chang-H