A Survey of Techniques For Improving Energy Efficiency in Embedded Computing Systems

Recent technological advances have greatly improved the performance and features of embedded systems. With the number of just mobile devices now reaching nearly equal to the population of earth, embedded systems have truly become ubiquitous. These trends, however, have also made the task of managing their power consumption extremely challenging. In recent years, several techniques have been proposed to address this issue. In this paper, we survey the techniques for managing power consumption of embedded systems. We discuss the need of power management and provide a classification of the techniques on several important parameters to highlight their similarities and differences. This paper is intended to help the researchers and application-developers in gaining insights into the working of power management techniques and designing even more efficient high-performance embedded systems of tomorrow

REAL-TIME ADAPTIVE PULSE COMPRESSION ON RECONFIGURABLE, SYSTEM-ON-CHIP (SOC) PLATFORMS

New radar applications need to perform complex algorithms and process a large quantity of data to generate useful information for the users. This situation has motivated the search for better processing solutions that include low-power high-performance processors, efficient algorithms, and high-speed interfaces. In this work, hardware implementation of adaptive pulse compression algorithms for real-time transceiver optimization is presented, and is based on a System-on-Chip architecture for reconfigurable hardware devices. This study also evaluates the performance of dedicated coprocessors as hardware accelerator units to speed up and improve the computation of computing-intensive tasks such matrix multiplication and matrix inversion, which are essential units to solve the covariance matrix. The tradeoffs between latency and hardware utilization are also presented. Moreover, the system architecture takes advantage of the embedded processor, which is interconnected with the logic resources through high-performance buses, to perform floating-point operations, control the processing blocks, and communicate with an external PC through a customized software interface. The overall system functionality is demonstrated and tested for real-time operations using a Ku-band testbed together with a low-cost channel emulator for different types of waveforms

FPGA-Based Software GNSS Receiver Design for Satellite Applications

Global Navigation Satellite System (GNSS) receiver technology has tremendous scope for satellite applications such as radio occultation, precise orbit determination and reflectometry. Spaceborne GNSS receivers are characterised by low power requirements, high processing speed and radiation resistant electronic components. Such sophisticated receivers, also called hardware GNSS receivers, are fabricated for specific applications and hence lack design flexibility. On the other hand, a software GNSS receiver allows easy design modifications without any hardware component replacement. Software receivers employ reconfigurable hardware elements called Field Programmable Gate Arrays (FPGAs). In this research, a low-power, low-cost software GNSS receiver has been designed and developed using a combination of a microprocessor and FPGA (System-on-Chip or SoC). The developed software GNSS receiver is capable of detecting GPS satellites, tracking them and computing receiver position estimates. Efficient task partitioning is achieved by implementing operations in both, the FPGA and the microprocessor. Also demonstrated is the improvement of processing speed by 20% when certain GNSS receiver operations are performed in the FPGA instead of the microprocessor

Digital FPGA Circuits Design for Real-Time Video Processing with Reference to Two Application Scenarios

In the present days of digital revolution, image and/or video processing has become a ubiquitous task: from mobile devices to special environments, the need for a real-time approach is everyday more and more evident. Whatever the reason, either for user experience in recreational or internet-based applications or for safety related timeliness in hard-real-time scenarios, the exploration of technologies and techniques which allow for this requirement to be satisfied is a crucial point. General purpose CPU or GPU software implementations of these applications are quite simple and widespread, but commonly do not allow high performance because of the high layering that separates high level languages and libraries, which enforce complicated procedures and algorithms, from the base architecture of the CPUs that offers only limited and basic (although rapidly executed) arithmetic operations. The most practised approach nowadays is based on the use of Very-Large-Scale Integrated (VLSI) digital electronic circuits. Field Programmable Gate Arrays (FPGAs) are integrated digital circuits designed to be configured after manufacturing, "on the field". They typically provide lower performance levels when compared to Application Specific Integrated Circuits (ASICs), but at a lower cost, especially when dealing with limited production volumes. Of course, on-the-field programmability itself (and re-programmability, in the vast majority of cases) is also a characteristic feature that makes FPGA more suitable for applications with changing specifications where an update of capabilities may be a desirable benefit. Moreover, the time needed to fulfill the design cycle for FPGA-based circuits (including of course testing and debug speed) is much reduced when compared to the design flow and time-to-market of ASICs. In this thesis work, we will see (Chapter 1) some common problems and strategies involved with the use of FPGAs and FPGA-based systems for Real Time Image Processing and Real Time Video Processing (in the following alsoindicated interchangeably with the acronym RTVP); we will then focus, in particular, on two applications. Firstly, Chapter 2 will cover the implementation of a novel algorithm for Visual Search, known as CDVS, which has been recently standardised as part of the MPEG-7 standard. Visual search is an emerging field in mobile applications which is rapidly becoming ubiquitous. However, typically, algorithms for this kind of applications are connected with a high leverage on computational power and complex elaborations: as a consequence, implementation efficiency is a crucial point, and this generally results in the need for custom designed hardware. Chapter 3 will cover the implementation of an algorithm for the compression of hyperspectral images which is bit-true compatible with the CCSDS-123.0 standard algorithm. Hyperspectral images are three dimensional matrices in which each 2D plane represents the image, as captured by the sensor, in a given spectral band: their size may range from several millions of pixels up to billions of pixels. Typical scenarios of use of hyperspectral images include airborne and satellite-borne remote sensing. As a consequence, major concerns are the limitedness of both processing power and communication links bandwidth: thus, a proper compression algorithm, as well as the efficiency of its implementation, is crucial. In both cases we will first of all examine the scope of the work with reference to current state-of-the-art. We will then see the proposed implementations in their main characteristics and, to conclude, we will consider the primary experimental results

Software Defined Radio Implementation Of Ds-Cdma In Inter-Satellite Communications For Small Satellites

The increased usage of CubeSats recently has changed the communication philosophy from long-range point-to-point propagations to a multi-hop network of small orbiting nodes. Separating system tasks into many dispersed satellites can increase system survivability, versatility, configurability, adaptability, and autonomy. Inter-satellite links (ISL) enable the satellites to exchange information and share resources while reducing the traffic load to the ground. Establishment and stability of the ISL are impacted by factors such as the satellite orbit and attitude, antenna configuration, constellation topology, mobility, and link range. Software Defined Radio (SDR) is beginning to be heavily used in small satellite communications for applications such as base stations. A software-defined radio is a software program that does the functionality of a hardware system. The digital signal processing blocks are incorporated into the software giving it more flexibility and modulation. With this, the idea of a remote upgrade from the ground as well as the potential to accommodate new applications and future services without hardware changes is very promising. Realizing this, my idea is to create an inter-satellite link using software defined radio. The advantages of this are higher data rates, modification of operating frequencies, possibility of reaching higher frequency bands for higher throughputs, flexible modulation, demodulation and encoding schemes, and ground modifications. However, there are several challenges in utilizing the software-defined radio to create an inter-satellite link communication for small satellites. In this paper, we designed and implemented a multi-user inter-satellite communication network using SDRs, where Code Division Multiple Access (CDMA) technique is utilized to manage the multiple accesses to shared communication channel among the satellites. This model can be easily reconfigured to support any encoding/decoding, modulation, and other signal processing schemes

Software Defined Radio Implementation Of Ds-Cdma In Inter-Satellite Communications For Small Satellites

The increased usage of CubeSats recently has changed the communication philosophy from long-range point-to-point propagations to a multi-hop network of small orbiting nodes. Separating system tasks into many dispersed satellites can increase system survivability, versatility, configurability, adaptability, and autonomy. Inter-satellite links (ISL) enable the satellites to exchange information and share resources while reducing the traffic load to the ground. Establishment and stability of the ISL are impacted by factors such as the satellite orbit and attitude, antenna configuration, constellation topology, mobility, and link range. Software Defined Radio (SDR) is beginning to be heavily used in small satellite communications for applications such as base stations. A software-defined radio is a software program that does the functionality of a hardware system. The digital signal processing blocks are incorporated into the software giving it more flexibility and modulation. With this, the idea of a remote upgrade from the ground as well as the potential to accommodate new applications and future services without hardware changes is very promising. Realizing this, my idea is to create an inter-satellite link using software defined radio. The advantages of this are higher data rates, modification of operating frequencies, possibility of reaching higher frequency bands for higher throughputs, flexible modulation, demodulation and encoding schemes, and ground modifications. However, there are several challenges in utilizing the software-defined radio to create an inter-satellite link communication for small satellites. In this paper, we designed and implemented a multi-user inter-satellite communication network using SDRs, where Code Division Multiple Access (CDMA) technique is utilized to manage the multiple accesses to shared communication channel among the satellites. This model can be easily reconfigured to support any encoding/decoding, modulation, and other signal processing schemes

Heterogeneity-aware scheduling and data partitioning for system performance acceleration

Over the past decade, heterogeneous processors and accelerators have become increasingly prevalent in modern computing systems. Compared with previous homogeneous parallel machines, the hardware heterogeneity in modern systems provides new opportunities and challenges for performance acceleration. Classic operating systems optimisation problems such as task scheduling, and application-specific optimisation techniques such as the adaptive data partitioning of parallel algorithms, are both required to work together to address hardware heterogeneity. Significant effort has been invested in this problem, but either focuses on a specific type of heterogeneous systems or algorithm, or a high-level framework without insight into the difference in heterogeneity between different types of system. A general software framework is required, which can not only be adapted to multiple types of systems and workloads, but is also equipped with the techniques to address a variety of hardware heterogeneity. This thesis presents approaches to design general heterogeneity-aware software frameworks for system performance acceleration. It covers a wide variety of systems, including an OS scheduler targeting on-chip asymmetric multi-core processors (AMPs) on mobile devices, a hierarchical many-core supercomputer and multi-FPGA systems for high performance computing (HPC) centers. Considering heterogeneity from on-chip AMPs, such as thread criticality, core sensitivity, and relative fairness, it suggests a collaborative based approach to co-design the task selector and core allocator on OS scheduler. Considering the typical sources of heterogeneity in HPC systems, such as the memory hierarchy, bandwidth limitations and asymmetric physical connection, it proposes an application-specific automatic data partitioning method for a modern supercomputer, and a topological-ranking heuristic based schedule for a multi-FPGA based reconfigurable cluster. Experiments on both a full system simulator (GEM5) and real systems (Sunway Taihulight Supercomputer and Xilinx Multi-FPGA based clusters) demonstrate the significant advantages of the suggested approaches compared against the state-of-the-art on variety of workloads."This work is supported by St Leonards 7th Century Scholarship and Computer Science PhD funding from University of St Andrews; by UK EPSRC grant Discovery: Pattern Discovery and Program Shaping for Manycore Systems (EP/P020631/1)." -- Acknowledgement

Survey of FPGA applications in the period 2000 – 2015 (Technical Report)

Romoth J, Porrmann M, Rückert U. Survey of FPGA applications in the period 2000 – 2015 (Technical Report).; 2017.Since their introduction, FPGAs can be seen in more and more different fields of applications. The key advantage is the combination of software-like flexibility with the performance otherwise common to hardware. Nevertheless, every application field introduces special requirements to the used computational architecture. This paper provides an overview of the different topics FPGAs have been used for in the last 15 years of research and why they have been chosen over other processing units like e.g. CPUs

Design and implementation of an SDR-based multi-frequency ground-based SAR system

Synthetic Aperture Radar (SAR) has proven a valuable tool in the monitoring of the Earth, either at a global or local scales. SAR is a coherent radar system able to image extended areas with high resolution, and finds applications in many areas such as forestry, agriculture, mining, structure inspection or security operations. Although space-borne SAR systems can image extended areas, their main limitation is the long revisit times, which are not suitable for applications where the target experiments rapid changes, in the scale of minutes to few days. GBSAR systems have proven useful to fill this revisit time gap by imaging relatively small areas continuously, with extensions usually smaller than a few square kilometers. Ground Based SAR (GBSAR) systems have been used extensively for the monitoring of slope instability, and are a common tool in the mining sector. The development of the GBSAR is relatively recent, and various developments have taken place since the 2000s, transitioning from the usage of Vector Network Analyzers (VNAs) to custom radar cores tailored for this application. This transition is accompanied by a reduction in cost, but at the same time is accompanied by a loss of operational flexibility. Specifically, most GBSAR sensors now operate at a single frequency, losing the value of the multi-band operation that VNAs provided. This work is motivated by the idea that it is worth to use the value of multi-frequency GBSAR measurements, while maintaining a limited system cost. In order to implement a GBSAR with these characteristics, it is realized that Software Defined Radio (SDR) devices are a good option for fast and flexible implementation of broadband transceivers. This thesis details the design and implementation process of an SDR-based Frequency Modulated Continuous Wave (FMCW) GBSAR system from the ground up, presenting the main issues related with the usage of the most common SDR analog architecture, the Zero-IF transceiver. The main problem is determined to be the behavior of spurs related to IQ imbalances of the analog transceiver with the FMCW demodulation process. Two effective techniques to overcome these issues, the Super Spatial Variant Apodization (SSVA) and the Short Time Fourier Transform (STFT) signal reconstruction techniques, are implemented and tested. The thesis also deals with the digital implementation of the signal generator and digital receiver, which are implemented on top of an RF Network-on-Chip (RFNoC) architecture in the SDR Field Programmable Gate Array (FPGA). Another important aspect of this work is the development of an radiofrequency front-end that extends the capabilities of the SDR, implementing filtering, amplification, leakage mitigation and up-conversion to X-band. Finally, a set of test campaigns is described, in which the operation of the system is verified and the value of multi-frequency GBSAR observations is shown.El radar d'obertura sintètica (SAR) ha demostrat ser una eina valuosa en el monitoratge de la Terra, sigui a escala global o local. El SAR és un sistema de radar coherent capaç d’obtenir imatges de zones extenses amb alta resolució i té aplicacions en moltes àrees com la silvicultura, l’agricultura, la mineria, la inspecció d’estructures o les operacions de seguretat. Tot i que els sistemes SAR embarcats en plataformes orbitals poden obtenir imatges d'àrees extenses, la seva principal limitació és el temps de revisita, que no són adequats per a aplicacions on l'objectiu experimenta canvis ràpids, en una escala de minuts a pocs dies. Els sistemes GBSAR han demostrat ser útils per omplir aquesta bretxa de temps, obtenint imatges d'àrees relativament petites de manera contínua, amb extensions generalment inferiors a uns pocs quilòmetres quadrats. Els sistemes SAR terrestres (GBSAR) s’han utilitzat àmpliament per al control de la inestabilitat de talussos i esllavissades i són una eina comuna al sector miner. El desenvolupament del GBSAR és relativament recent i s’han produït diversos desenvolupaments des de la dècada de 2000, passant de l’ús d’analitzadors de xarxes vectorials (VNA) a nuclis de radar personalitzats i adaptats a aquesta aplicació. Aquesta transició s’acompanya d’una reducció del cost, però al mateix temps d’una pèrdua de flexibilitat operativa. Concretament, la majoria dels sensors GBSAR funcionen a una única freqüència, perdent el valor de l’operació en múltiples bandes que proporcionaven els VNA. Aquesta tesi està motivada per la idea de recuperar el valor de les mesures GBSAR multifreqüència, mantenint un cost del sistema limitat. Per tal d’implementar un GBSAR amb aquestes característiques, s’adona que els dispositius de ràdio definida per software (SDR) són una bona opció per a la implementació ràpida i flexible dels transceptors de banda ampla. Aquesta tesi detalla el procés de disseny i implementació d’un sistema GBSAR d’ona contínua modulada en freqüència (FMCW) basat en la tecnologia SDR, presentant els principals problemes relacionats amb l’ús de l’arquitectura analògica de SDR més comuna, el transceptor Zero-IF. Es determina que el problema principal és el comportament dels espuris relacionats amb el balanç de les cadenes de fase i quadratura del transceptor analògic amb el procés de desmodulació FMCW. S’implementen i comproven dues tècniques efectives per minimitzar aquests problemes basades en la reconstrucció de la senyal contaminada per espuris: la tècnica anomenada Super Spatial Variant Apodization (SSVA) i una tècnica basada en la transformada de Fourier amb finestra (STFT). La tesi també tracta la implementació digital del generador de senyal i del receptor digital, que s’implementen sobre una arquitectura RF Network-on-Chip (RFNoC). Un altre aspecte important d’aquesta tesi és el desenvolupament d’un front-end de radiofreqüència que amplia les capacitats de la SDR, implementant filtratge, amplificació, millora de l'aïllament entre transmissió i recepció i conversió a banda X. Finalment, es descriu un conjunt de campanyes de prova en què es verifica el funcionament del sistema i es mostra el valor de les observacions GBSAR multifreqüència

NASA Tech Briefs, May 2011

Topics covered include: 1) Method to Estimate the Dissolved Air Content in Hydraulic Fluid; 2) Method for Measuring Collimator-Pointing Sensitivity to Temperature Changes; 3) High-Temperature Thermometer Using Cr-Doped GdAlO3 Broadband Luminescence; 4)Metrology Arrangement for Measuring the Positions of Mirrors of a Submillimeter Telescope; 5) On-Wafer S-Parameter Measurements in the 325-508-GHz Band; 6) Reconfigurable Microwave Phase Delay Element for Frequency Reference and Phase-Shifter Applications; 7) High-Speed Isolation Board for Flight Hardware Testing; 8) High-Throughput, Adaptive FFT Architecture for FPGA-Based Spaceborne Data Processors; 9) 3D Orbit Visualization for Earth-Observing Missions; 10) MaROS: Web Visualization of Mars Orbiting and Landed Assets; 11) RAPID: Collaborative Commanding and Monitoring of Lunar Assets; 12) Image Segmentation, Registration, Compression, and Matching; 13) Image Calibration; 14) Rapid ISS Power Availability Simulator; 15) A Method of Strengthening Composite/Metal Joints; 16) Pre-Finishing of SiC for Optical Applications; 17) Optimization of Indium Bump Morphology for Improved Flip Chip Devices; 18) Measuring Moisture Levels in Graphite Epoxy Composite Sandwich Structures; 19) Marshall Convergent Spray Formulation Improvement for High Temperatures; 20) Real-Time Deposition Monitor for Ultrathin Conductive Films; 21) Optimized Li-Ion Electrolytes Containing Triphenyl Phosphate as a Flame-Retardant Additive; 22) Radiation-Resistant Hybrid Lotus Effect for Achieving Photoelectrocatalytic Self-Cleaning Anticontamination Coatings; 23) Improved, Low-Stress Economical Submerged Pipeline; 24) Optical Fiber Array Assemblies for Space Flight on the Lunar Reconnaissance Orbiter; 25) Local Leak Detection and Health Monitoring of Pressurized Tanks; 26) Dielectric Covered Planar Antennas at Submillimeter Wavelengths for Terahertz Imaging; 27) Automated Cryocooler Monitor and Control System; 28) Broadband Achromatic Phase Shifter for a Nulling Interferometer; 29) Super Dwarf Wheat for Growth in Confined Spaces; 30) Fine Guidance Sensing for Coronagraphic Observatories; 31) Single-Antenna Temperature- and Humidity-Sounding Microwave Receiver; 32) Multi-Wavelength, Multi-Beam, and Polarization-Sensitive Laser Transmitter for Surface Mapping; 33) Optical Communications Link to Airborne Transceiver; 34) Ascent Heating Thermal Analysis on Spacecraft Adaptor Fairings; 35) Entanglement in Self-Supervised Dynamics; 36) Prioritized LT Codes; 37) Fast Image Texture Classification Using Decision Trees; 38) Constraint Embedding Technique for Multibody System Dynamics; 39) Improved Systematic Pointing Error Model for the DSN Antennas; 40) Observability and Estimation of Distributed Space Systems via Local Information-Exchange Networks; 41) More-Accurate Model of Flows in Rocket Injectors; 42) In-Orbit Instrument-Pointing Calibration Using the Moon as a Target; 43) Reliability of Ceramic Column Grid Array Interconnect Packages Under Extreme Temperatures; 44) Six Degrees-of-Freedom Ascent Control for Small-Body Touch and Go; and 45) Optical-Path-Difference Linear Mechanism for the Panchromatic Fourier Transform Spectrometer