Overcoming the Challenges for Multichip Integration: A Wireless Interconnect Approach

The physical limitations in the area, power density, and yield restrict the scalability of the single-chip multicore system to a relatively small number of cores. Instead of having a large chip, aggregating multiple smaller chips can overcome these physical limitations. Combining multiple dies can be done either by stacking vertically or by placing side-by-side on the same substrate within a single package. However, in order to be widely accepted, both multichip integration techniques need to overcome significant challenges. In the horizontally integrated multichip system, traditional inter-chip I/O does not scale well with technology scaling due to limitations of the pitch. Moreover, to transfer data between cores or memory components from one chip to another, state-of-the-art inter-chip communication over wireline channels require data signals to travel from internal nets to the peripheral I/O ports and then get routed over the inter-chip channels to the I/O port of the destination chip. Following this, the data is finally routed from the I/O to internal nets of the target chip over a wireline interconnect fabric. This multi-hop communication increases energy consumption while decreasing data bandwidth in a multichip system. On the other hand, in vertically integrated multichip system, the high power density resulting from the placement of computational components on top of each other aggravates the thermal issues of the chip leading to degraded performance and reduced reliability. Liquid cooling through microfluidic channels can provide cooling capabilities required for effective management of chip temperatures in vertical integration. However, to reduce the mechanical stresses and at the same time, to ensure temperature uniformity and adequate cooling competencies, the height and width of the microchannels need to be increased. This limits the area available to route Through-Silicon-Vias (TSVs) across the cooling layers and make the co-existence and co-design of TSVs and microchannels extreamly challenging. Research in recent years has demonstrated that on-chip and off-chip wireless interconnects are capable of establishing radio communications within as well as between multiple chips. The primary goal of this dissertation is to propose design principals targeting both horizontally and vertically integrated multichip system to provide high bandwidth, low latency, and energy efficient data communication by utilizing mm-wave wireless interconnects. The proposed solution has two parts: the first part proposes design methodology of a seamless hybrid wired and wireless interconnection network for the horizontally integrated multichip system to enable direct chip-to-chip communication between internal cores. Whereas the second part proposes a Wireless Network-on-Chip (WiNoC) architecture for the vertically integrated multichip system to realize data communication across interlayer microfluidic coolers eliminating the need to place and route signal TSVs through the cooling layers. The integration of wireless interconnect will significantly reduce the complexity of the co-design of TSV based interconnects and microchannel based interlayer cooling. Finally, this dissertation presents a combined trade-off evaluation of such wireless integration system in both horizontal and vertical sense and provides future directions for the design of the multichip system

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Contactless Test Access Mechanism for 3D IC

3D IC integration presents many advantages over the current 2D IC integration. It has the potential to reduce the power consumption and the physical size while supporting higher bandwidth and processing speed. Through Silicon Via’s (TSVs) are vertical interconnects between different layers of 3D ICs with a typical 5μm diameter and 50μm length. To test a 3D IC, an access mechanism is needed to apply test vectors to TSVs and observe their responses. However, TSVs are too small for access by current wafer probes and direct TSV probing may affect their physical integrity. In addition, the probe needles for direct TSV probing must be cleaned or replaced frequently. Contactless probing method resolves most of the TSV probing problems and can be employed for small-pitch TSVs. In this dissertation, contactless test access mechanisms for 3D IC have been explored using capacitive and inductive coupling techniques. Circuit models for capacitive and inductive communication links are extracted using 3D full-wave simulations and then circuit level simulations are carried out using Advanced Design System (ADS) design environment to verify the results. The effects of cross-talk and misalignment on the communication link have been investigated. A contactless TSV probing method using capacitive coupling is proposed and simulated. A prototype was fabricated using TSMC 65nm CMOS technology to verify the proposed method. The measurement results on the fabricated prototype show that this TSV probing scheme presents -55dB insertion loss at 1GHz frequency and maintains higher than 35dB signal-to-noise ratio within 5µm distance. A microscale contactless probe based on the principle of resonant inductive coupling has also been designed and simulated. Experimental measurements on a prototype fabricated in TSMC 65nm CMOS technology indicate that the data signal on the TSV can be reconstructed when the distance between the TSV and the probe remains less than 15µm

A fast and precise tool for multi-layer planar coil self-inductance calculation

An open-source tool that allows for a fast and precise analytical calculation of multi-layer planar coils self-inductance, without any geometry limitation is proposed here. The process of designing and simulating planar coils to achieve reliable results is commonly limited on accuracy and or geometry, or are too time-consuming and expensive, thus a tool to speed up this design process is desired. The model is based on Grover equations, valid for any geometry. The validation of the tool was performed through the comparison with experimental measurements, Finite Element Model (FEM) simulations, and the main analytical methods usually used in literature, with errors registered to be below 2.5%, when compared to standard FEM simulations, and when compared to experimental measurements they are below 10% in the case of the 1-layer coils, and below 5% in the 2-layer coils (without taking into consideration the coil connectors). The proposed model offers a new approach to the calculation of the self-inductance of planar coils of several layers that combines precision, speed, independence of geometry, easy interaction, and no need for extra resources.This work is supported by: European Structural and Investment Funds in the FEDER component, through the Operational Competitiveness and Internationalization Programme (COMPETE 2020) [Project nº 037902; Funding Reference: POCI-01-0247-FEDER-037902]. The work of Andreia Faria was funded by FCT—Fundação para a Ciência e Tecnologia under Grant PD/BD/128142/2016. The work of Carlos Ferreira was supported by the Fundação para a Ciência e Tecnologia (FCT) under Grant PD/BDE/135102/2017

A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks

Designing a low power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Resonant clock networks are considered efficient low power alternatives to con- ventional clock distribution schemes. These networks utilize ad- ditional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. Test is another complex task for 3-D ICs, where pre-bond test is a prerequisite. Contactless test has been considered as an alternative for conventional test methods. This paper, consequently, introduces a design method- ology for resonant 3-D clock networks that supports wireless pre- bond testing through the use of inductive links. By employing the inductors comprising the LC tanks of the resonant clock net- works as the receiver circuit for the links, the need for additional circuits and/or interconnect resources during pre-bond test is essentially eliminated. The proposed technique produces low power and pre-bond testable 3-D clock distribution networks. Simulation results indicate 98.5% and 99% decrease in the area overhead and power consumed by the contactless testing method as compared to existing methods

Wireless Sensors for Health Monitoring of Marine Structures and Machinery

Remote structural and machinery health monitoring (SMHM) of marine structures such as ships, oil and gas rigs, freight container terminals, and marine energy platforms can ensure their reliability. However, the wired sensors currently used in these applications are difficult and expensive to install and maintain. Wireless Sensor Networks (WSN) can potentially replace them but there are significant capability gaps that currently prevent their long-term deployment in the harsh marine environment and the structurally-complex, compartmentalised, all-metal scenarios with high volume occupancy of piping, ducting and operational machinery represented by marine structures. These gaps are in sensing, processing and communication hardware and firmware capabilities, reduction of power consumption, hardware assembly and packaging for reliability in the marine environment, reliability of wireless connectivity in the complex metal structures, and software for WSN deployment planning in the marine environment. Taken together, these gaps highlight the need for a systems integration methodology for marine SMHM and this is the focus of the research presented in this thesis. The research takes an applied approach by first designing the hardware and firmware for two wireless sensing modules specifically for marine SMHM, one a novel eddy-current-based 3D module for measuring multi-axis metal structural displacement, the second a fully integrated module for monitoring of structure and machinery reliability. The research then addresses module assembly and packaging methods to ensure reliability in the marine environment, the development of an efficient methodology for characterising the reliability of wireless connectivity in complex metal structures, and development of user interface software for planning WSN deployment and for managing the collection of WSN data. These are then individually and collectively characterised and tested for performance and reliability in laboratory, land-based and marine deployments. In addition to the research outcomes in each of these individual aspects, the overall research outcome represents a systems integration methodology that now allows deployment, with a high expectation of reliability of marine SMHM WSNs

BiCMOS Millimetre-wave low-noise amplifier

Abstract: Please refer to full text to view abstract.D.Phil. (Electrical and Electronic Engineering

High Speed Test Interface Module Using MEMS Technology

With the transient frequency of available CMOS technologies exceeding hundreds of gigahertz and the increasing complexity of Integrated Circuit (IC) designs, it is now apparent that the architecture of current testers needs to be greatly improved to keep up with the formidable challenges ahead. Test requirements for modern integrated circuits are becoming more stringent, complex and costly. These requirements include an increasing number of test channels, higher test-speeds and enhanced measurement accuracy and resolution. In a conventional test configuration, the signal path from Automatic Test Equipment (ATE) to the Device-Under-Test (DUT) includes long traces of wires. At frequencies above a few gigahertz, testing integrated circuits becomes a challenging task. The effects on transmission lines become critical requiring impedance matching to minimize signal reflection. AC resistance due to the skin effect and electromagnetic coupling caused by radiation can also become important factors affecting the test results. In the design of a Device Interface Board (DIB), the greater the physical separation of the DUT and the ATE pin electronics, the greater the distortion and signal degradation. In this work, a new Test Interface Module (TIM) based on MEMS technology is proposed to reduce the distance between the tester and device-under-test by orders of magnitude. The proposed solution increases the bandwidth of test channels and reduces the undesired effects of transmission lines on the test results. The MEMS test interface includes a fixed socket and a removable socket. The removable socket incorporates MEMS contact springs to provide temporary with the DUT pads and the fixed socket contains a bed of micro-pins to establish electrical connections with the ATE pin electronics. The MEMS based contact springs have been modified to implement a high-density wafer level test probes for Through Silicon Vias (TSVs) in three dimensional integrated circuits (3D-IC). Prototypes have been fabricated using Silicon On Insulator SOI wafer. Experimental results indicate that the proposed architectures can operate up to 50 GHz without much loss or distortion. The MEMS probes can also maintain a good elastic performance without any damage or deformation in the test phase

High-performance wireless power and data transfer interface for implantable medical devices

D’importants progès ont été réalisés dans le développement des systèmes biomédicaux implantables grâce aux dernières avancées de la microélectronique et des technologies sans fil. Néanmoins, ces appareils restent difficiles à commercialier. Cette situation est due particulièrement à un manque de stratégies de design capable supporter les fonctionnalités exigées, aux limites de miniaturisation, ainsi qu’au manque d’interface sans fil à haut débit fiable et faible puissance capable de connecter les implants et les périphériques externes. Le nombre de sites de stimulation et/ou d’électrodes d’enregistrement retrouvés dans les dernières interfaces cerveau-ordinateur (IMC) ne cesse de croître afin d’augmenter la précision de contrôle, et d’améliorer notre compréhension des fonctions cérébrales. Ce nombre est appelé à atteindre un millier de site à court terme, ce qui exige des débits de données atteingnant facilement les 500 Mbps. Ceci étant dit, ces travaux visent à élaborer de nouvelles stratégies innovantes de conception de dispositifs biomédicaux implantables afin de repousser les limites mentionnées ci-dessus. On présente de nouvelles techniques faible puissance beaucoup plus performantes pour le transfert d’énergie et de données sans fil à haut débit ainsi que l’analyse et la réalisation de ces dernières grâce à des prototypes microélectroniques CMOS. Dans un premier temps, ces travaux exposent notre nouvelle structure multibobine inductive à résonance présentant une puissance sans fil distribuée uniformément pour alimenter des systèmes miniatures d’étude du cerveaux avec des models animaux en ilberté ainsi que des dispositifs médicaux implantbles sans fil qui se caractérisent par une capacité de positionnement libre. La structure propose un lien de résonance multibobines inductive, dont le résonateur principal est constitué d’une multitude de résonateurs identiques disposés dans une matrice de bobines carrées. Ces dernières sont connectées en parallèle afin de réaliser des surfaces de puissance (2D) ainsi qu’une chambre d’alimentation (3D). La chambre proposée utilise deux matrices de résonateurs de base, mises face à face et connectés en parallèle afin d’obtenir une distribution d’énergie uniforme en 3D. Chaque surface comprend neuf bobines superposées, connectées en parallèle et réailsées sur une carte de circuit imprimé deux couches FR4. La chambre dispose d’un mécanisme naturel de localisation de puissance qui facilite sa mise en oeuvre et son fonctionnement. En procédant ainsi, nous évitons la nécessité d’une détection active de l’emplacement de la charge et le contrôle d’alimentation. Notre approche permet à cette surface d’alimentation unique de fournir une efficacité de transfert de puissance (PTE) de 69% et une puissance délivrée à la charge (PDL) de 120 mW, pour une distance de séparation de 4 cm, tandis que le prototype de chambre complet fournit un PTE uniforme de 59% et un PDL de 100 mW en 3D, partout à l’intérieur de la chambre avec un volume de chambre de 27 × 27 × 16 cm3. Une étape critique avant d’utiliser un dispositif implantable chez les humains consiste à vérifier ses fonctionnalités sur des sujets animaux. Par conséquent, la chambre d’énergie sans fil conçue sera utilisée afin de caractériser les performances d’ une interface sans fil de transmisison de données dans un environnement réaliste in vivo avec positionement libre. Un émetteur-récepteur full-duplex (FDT) entièrement intégré qui se caractérise par sa faible puissance est conçu pour réaliser une interfaces bi-directionnelles (stimulation et enregistrement) avec des débits asymétriques: des taux de tramnsmission plus élevés sont nécessaires pour l’enregistrement électrophysiologique multicanal (signaux de liaison montante) alors que les taux moins élevés sont utilisés pour la stimulation (les signaux de liaison descendante). L’émetteur (TX) et le récepteur (RX) se partagent une seule antenne afin de réduire la taille de l’implant. L’émetteur utilise la radio ultra-large bande par impulsions (IR-UWB) basée sur l’approche edge combining et le RX utilise la bande ISM (Industrielle, Scientifique et Médicale) de fréquence central 2.4 GHz et la modulation on-off-keying (OOK). Une bonne isolation (> 20 dB) est obtenue entre le TX et le RX grâce à 1) la mise en forme les impulsions émises dans le spectre UWB non réglementée (3.1-7 GHz), et 2) le filtrage espace-efficace (évitant l’utilisation d’un circulateur ou d’un diplexeur) du spectre du lien de communication descendant directement au niveau de l’ amplificateur à faible bruit (LNA). L’émetteur UWB 3.1-7 GHz utilise un e modultion OOK ainsi qu’une modulation par déplacement de phase (BPSK) à seulement 10.8 pJ / bits. Le FDT proposé permet d’atteindre 500 Mbps de débit de données en lien montant et 100 Mbps de débit de données de lien descendant. Il est entièrement intégré dans un procédé TSMC CMOS 0.18 um standard et possède une taille totale de 0.8 mm2. La consommation totale d’énergie mesurée est de 10.4 mW (5 mW pour RX et 5.4 mW pour TX au taux de 500 Mbps).In recent years, there has been major progress on implantable biomedical systems that support most of the functionalities of wireless implantable devices. Nevertheless, these devices remain mostly restricted to be commercialized, in part due to weakness of a straightforward design to support the required functionalities, limitation on miniaturization, and lack of a reliable low-power high data rate interface between implants and external devices. This research provides novel strategies on the design of implantable biomedical devices that addresses these limitations by presenting analysis and techniques for wireless power transfer and efficient data transfer. The first part of this research includes our proposed novel resonance-based multicoil inductive power link structure with uniform power distribution to wirelessly power up smart animal research systems and implanted medical devices with high power efficiency and free positioning capability. The proposed structure consists of a multicoil resonance inductive link, which primary resonator array is made of several identical resonators enclosed in a scalable array of overlapping square coils that are connected in parallel and arranged in power surface (2D) and power chamber (3D) configurations. The proposed chamber uses two arrays of primary resonators, facing each other, and connected in parallel to achieve uniform power distribution in 3D. Each surface includes 9 overlapped coils connected in parallel and implemented into two layers of FR4 printed circuit board. The chamber features a natural power localization mechanism, which simplifies its implementation and eases its operation by avoiding the need for active detection of the load location and power control mechanisms. A single power surface based on the proposed approach can provide a power transfer efficiency (PTE) of 69% and a power delivered to the load (PDL) of 120 mW, for a separation distance of 4 cm, whereas the complete chamber prototype provides a uniform PTE of 59% and a PDL of 100 mW in 3D, everywhere inside the chamber with a chamber size of 27×27×16 cm3. The second part of this research includes our proposed novel, fully-integrated, low-power fullduplex transceiver (FDT) to support bi-directional neural interfacing applications (stimulating and recording) with asymmetric data rates: higher rates are required for recording (uplink signals) than stimulation (downlink signals). The transmitter (TX) and receiver (RX) share a single antenna to reduce implant size. The TX uses impulse radio ultra-wide band (IR-UWB) based on an edge combining approach, and the RX uses a novel 2.4-GHz on-off keying (OOK) receiver. Proper isolation (> 20 dB) between the TX and RX path is implemented 1) by shaping the transmitted pulses to fall within the unregulated UWB spectrum (3.1-7 GHz), and 2) by space-efficient filtering (avoiding a circulator or diplexer) of the downlink OOK spectrum in the RX low-noise amplifier (LNA). The UWB 3.1-7 GHz transmitter using OOK and binary phase shift keying (BPSK) modulations at only 10.8 pJ/bit. The proposed FDT provides dual band 500 Mbps TX uplink data rate and 100 Mbps RX downlink data rate. It is fully integrated on standard TSMC 0.18 nm CMOS within a total size of 0.8 mm2. The total power consumption measured 10.4 mW (5 mW for RX and 5.4 mW for TX at the rate of 500 Mbps)